Memory circuit arrangement utilizing one-transistor-per-bit memo

Details Memory circuit arrangement utilizing one-transistor-per-bit memo Memory circuit arrangement utilizing one-transistor-per-bit memo

1977-05-18

1979-01-02

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365154, 365207, 365186, 307238, G11C 1140

Patent

active

041330498

ABSTRACT:
A memory circuit arrangement employing one-transistor-per-bit memory cells in which differential sense amplifiers are utilized for detecting the state of the stored bits. First and second digit lines are arranged substantially parallel to and adjacent to each other and first and second parallel word lines are arranged substantially at right angles to the digit lines. Memory cells are connected at each cross point between the digit lines and the word lines.

REFERENCES:
patent: 3882326 (1975-05-01), Kruggle
patent: 4031522 (1977-06-01), Reed et al.

Affiliated with

Also associated with

Rating

Memory circuit arrangement utilizing one-transistor-per-bit memo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory circuit arrangement utilizing one-transistor-per-bit memo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit arrangement utilizing one-transistor-per-bit memo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1520832