Memory circuit arrangement and method for the production...

Details Memory circuit arrangement and method for the production... Memory circuit arrangement and method for the production...

2011-08-23

2011-08-23

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C438S107000, C257SE25030, C257SE23062

Reexamination Certificate

active

08004869

ABSTRACT:
A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

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patent: 7460385 (2008-12-01), Gruber et al.
patent: 7764530 (2010-07-01), Gruber et al.
patent: 2001/0053223 (2001-12-01), Ishibashi et al.
patent: 2002/0050634 (2002-05-01), Han
patent: 2004/0056682 (2004-03-01), Wada

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