Memory circuit architecture

Details Memory circuit architecture Memory circuit architecture

1999-10-22

2001-03-27

Tran, Andrew (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

Reexamination Certificate

active

06208551

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory cells. More specifically, the present invention relates to memory cells of DRAM type compatible with a method of manufacturing a device incorporating such a memory and CMOS components.
2. Discussion of the Related Art
Conventionally, a DRAM appears as an array of columns and rows at the intersections of which are memory cells formed of a memory element, typically a capacitor, and of a switch for controlling this memory element, typically a MOS transistor.
FIG. 1
shows a portion of an equivalent diagram of such a memory. More specifically,
FIG. 1
15
illustrates the equivalent electric diagram of one of the memory rows. Among the n cells of the considered row, the first and last memory cells
1
and n have been shown. Cells
1
and n respectively include a capacitor C
1
, Cn, a first electrode of which is connected to the drain of a respective control transistor M
1
, Mn, and a second electrode of which is common to the n cells. The gate of transistor M
1
, Mn is connected to a word line WL
1
, WLn of the considered cell and its source is connected to a bit line BL
1
, BLn, of the considered cell. The drain/substrate junctions of each of transistors M
1
, Mn, shown in
FIG. 1
by diodes D
1
, Dn, ensure the storing of the information in memory element C
1
, Cn when the considered cell is not addressed in the write mode.
A conventional memory array includes a number n of rows and a number m of columns. IThe simple case in which n and m are equal, for example, n=m=1024, will be considered hereafter. Then, for each of the rows, identical to that shown in
FIG. 1
, the n−1 other rows of n memory cells form an equivalent capacitor Ceq, a first electrode of which is common to the common electrode of the n memory cells of the selected row, and a second electrode of which is grounded.
The electrode common to the n elements C
1
, Cn of the considered row and to capacitor Ceq is connectable to a first power supply capable of biasing it to a write potential Vdd when data have to be stored in a memory element.
Finally, outside write periods, the electrode common to the n elements C
1
, Cn of the considered row and to capacitor Ceq is precharged by a D.C. power supply V. Precharge voltage V may have any value, greater than the circuit ground potential and smaller than high write potential Vdd, but has to be very stable. A value equal to Vdd/2 is typically chosen, to decrease breakdown risks for the inter-electrode oxide during a switching to the ground potential as tile row is deselected.
A disadvantage of this type of structure is that, upon variation of the charge of capacitors C
1
, Cn, a relatively high positive or negative current surge appears, for example on the order of 5 mA, for a relatively long duration, on the order of 3 ns, for a 1-megabit memory. A relatively large voltage difference then appears across the considered row, for example, on the order of 0.25 V. Then, given the great number of capacitors which can be charged at the same time, such a phenomenon can affect the supplies which have to withstand such a positive or negative surge. Similarly, the circuit ground, common to all elements, is affected by such surges. In an extreme case, the propagation of such disturbances can affect one or several memory nodes and cause corruption of the stored data.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a DRAM in which the power supplies and the ground are protected from charge variations of the memory elements.
To achieve this and other objects, the present invention provides a DRAM made in monolithic form, the cells of which each include a MOS transistor and a capacitor, a second electrode of which is common to all cells of a same row and is covered with an insulator, wherein the insulator is coated with independent conductive elements distributed on a same horizontal plane, two neighboring elements being biased to respective high and low levels.
According to an embodiment of the present invention, the low potential is the reference potential of the circuit in which the cell is formed.
According to an embodiment of the present invention, the high potential is the write potential of the memory cell.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.


REFERENCES:
patent: 5243209 (1993-09-01), Ishii
patent: 5393998 (1995-02-01), Ishii et al.
patent: 5739576 (1998-04-01), Shirley et al.
patent: 5801412 (1998-09-01), Tobita
patent: 5949705 (1999-09-01), Jun et al.

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