Memory circuit and method for processing a code to be loaded...

Details Memory circuit and method for processing a code to be loaded... Memory circuit and method for processing a code to be loaded...

2007-02-27

2007-02-27

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C714S718000, C365S094000, C365S189050

Reexamination Certificate

active

10989096

ABSTRACT:
A ROM-type memory is provided that includes a matrix of memory cells made up of rows and columns, with each row allowing storage of a page of MUX words of N bits. An address decoder decodes addresses in order to extract the page to be read. At the output of the matrix, N multiplexers are each coupled to the columns that correspond to one of the bits of the output stage. An N-bit output stage includes at least one inverter, with each of the inverters being connected to the output of one of the multiplexers so as to restore inverted values of information to be stored to correct values. The inverted values are stored in all of the memory cells of all of the columns coupled to the one multiplexer. Storing the inverted values makes it possible to store less “0” values within the matrix and further makes LVS testing of the ROM memory considerably easier. Also provided is a method for sequentially checking groups of memory cells.

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patent: 6563745 (2003-05-01), Ilkbahar
Winegarden, S, “Bus Architecture of a system on a chip with user-configureable system logic” in IEEE Journal of Solid-State Circuits, Mar. 2000, vol. 35, Issue 3, pp. 425-433.

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