Memory circuit and method for corrupting stored data

Details Memory circuit and method for corrupting stored data Memory circuit and method for corrupting stored data

2006-01-24

2006-01-24

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06990011

ABSTRACT:
A method and circuit are disclosed for an integrated circuit having one or more memory cells, each memory cell including first and second p-channel transistor and first and second n-channel transistors configured as cross-coupled logic inverters between first and second reference voltage levels during a normal mode of operation. Power control circuitry is coupled to a source terminal of the first p-channel transistor of each memory cell for providing to the first p-channel transistors the first reference voltage level during the normal mode of operation. This causes a first voltage less than the first reference voltage level to appear at the source terminal of the first p-channel transistors during a data corruption mode of operation wherein data stored in the one or more memory cells is corrupted.

REFERENCES:
patent: 5303190 (1994-04-01), Pelley, III
patent: 5668770 (1997-09-01), Itoh et al.
patent: 5724648 (1998-03-01), Shaughnessy et al.
patent: 5781482 (1998-07-01), Sakata

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