Static information storage and retrieval – Read/write circuit – Serial read/write
Patent
1995-06-07
1998-09-08
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Serial read/write
365233, 36523008, G11C 800
Patent
active
058055185
ABSTRACT:
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and ouput data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
REFERENCES:
patent: 3740723 (1973-06-01), Beausoleil et al.
patent: 3758761 (1973-09-01), Henrion
patent: 3771145 (1973-11-01), Wiener
patent: 3821715 (1974-06-01), Hoff et al.
patent: 3882470 (1975-05-01), Hunter
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3924241 (1975-12-01), Kronies
patent: 3956737 (1976-05-01), Ball
patent: 3962689 (1976-06-01), Brunson
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 3972028 (1976-07-01), Weber et al.
patent: 3975714 (1976-08-01), Weber et al.
patent: 3983537 (1976-09-01), Parsons et al.
patent: 4007452 (1977-02-01), Hoff
patent: 4038648 (1977-07-01), Chesley
patent: 4099231 (1978-07-01), Kotok et al.
patent: 4120048 (1978-10-01), Fuhrman
patent: 4152781 (1979-05-01), Aichelmann, Jr.
patent: 4191996 (1980-03-01), Chesley
patent: 4205373 (1980-05-01), Shah
patent: 4225947 (1980-09-01), Councill et al.
patent: 4247817 (1981-01-01), Heller
patent: 4249247 (1981-02-01), Patel
patent: 4286321 (1981-08-01), Baker et al.
patent: 4306298 (1981-12-01), McElroy
patent: 4315308 (1982-02-01), Jackson
patent: 4321695 (1982-03-01), Redwine et al.
patent: 4333142 (1982-06-01), Chesley
patent: 4355376 (1982-10-01), Gould
patent: 4373183 (1983-02-01), Means et al.
patent: 4375084 (1983-02-01), Urushibata
patent: 4385350 (1983-05-01), Hansen et al.
patent: 4388696 (1983-06-01), Test, II et al.
patent: 4415994 (1983-11-01), Ive et al.
patent: 4435792 (1984-03-01), Bechtolsheim
patent: 4443864 (1984-04-01), McElroy
patent: 4449207 (1984-05-01), Kung et al.
patent: 4468738 (1984-08-01), Hansen et al.
patent: 4470114 (1984-09-01), Gerhold
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4488218 (1984-12-01), Grimes
patent: 4493060 (1985-01-01), Varshney
patent: 4500905 (1985-02-01), Shibata
patent: 4509142 (1985-04-01), Childers
patent: 4519034 (1985-05-01), Smith et al.
patent: 4549283 (1985-10-01), McDermott, III
patent: 4558377 (1985-12-01), Collins et al.
patent: 4567579 (1986-01-01), Patel et al.
patent: 4581721 (1986-04-01), Gunawardana
patent: 4595923 (1986-06-01), McFarland, Jr.
patent: 4608669 (1986-08-01), Klara et al.
patent: 4608678 (1986-08-01), Threewitt
patent: 4618947 (1986-10-01), Tran et al.
patent: 4630193 (1986-12-01), Kris
patent: 4633441 (1986-12-01), Ishimoto
patent: 4646270 (1987-02-01), Voss
patent: 4649511 (1987-03-01), Gdula
patent: 4649516 (1987-03-01), Chung et al.
patent: 4654655 (1987-03-01), Kowalski
patent: 4664502 (1987-05-01), Kawashima
patent: 4667313 (1987-05-01), Pinkham et al.
patent: 4685089 (1987-08-01), Patel et al.
patent: 4706166 (1987-11-01), Go
patent: 4719627 (1988-01-01), Peterson et al.
patent: 4745548 (1988-05-01), Blahut
patent: 4764846 (1988-08-01), Go
patent: 4770640 (1988-09-01), Walter
patent: 4779089 (1988-10-01), Theus
patent: 4785394 (1988-11-01), Fischer
patent: 4789960 (1988-12-01), Willis
patent: 4796224 (1989-01-01), Kawai et al.
patent: 4811202 (1989-03-01), Schabowski
patent: 4818985 (1989-04-01), Ikeda
patent: 4833651 (1989-05-01), Seltzer et al.
patent: 4837682 (1989-06-01), Culler
patent: 4860198 (1989-08-01), Takenaka
patent: 4899316 (1990-02-01), Nagami
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4975763 (1990-12-01), Baudouin et al.
patent: 4999814 (1991-03-01), Hashimoto
patent: 5023488 (1991-06-01), Gunning
patent: 5093807 (1992-03-01), Hashimoto et al.
patent: 5179670 (1993-01-01), Farmwald et al.
patent: 5319755 (1994-06-01), Farmwald et al.
Bell Laboratories, Incorporated, Transmission Systems for Communications, 5th Edition, 1982, pp. 590-591.
Cole, Bernard C., "Motorola's Radical SRAM Design Speeds Systems 40%, Electronics", Jul. 23, 1987, pp. 66-68.
Hashimoto, Masashi et al., "A 20-ns 256K X 4 FIFO Memory", IEEE Journal of Solid-State Circuits, vol. 23, No. 2, Apr. 1988, pp. 490-499.
Hashimoto, Masashi et al., "A 20 ns 256K X 4 FIFO Memory", IEEE 1987 Custom Integrated Circuits Conference, May 4-7, 1987, pp. 315-318.
Horowitz, Mark et al., "MIPS-X: A 20-MIPS Peak, 32-bit Microprocessor with On-Chip Cache", IEEE Journal of Solid-Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 790-799.
Lineback, J. Robert, "System Snags Shouldn't Slow the Boom in Fast Static RAMS", Electronics, Jul. 23, 1987, pp. 60-62.
Miyaguchi et al., "A Field Store System With Single 1Mbit Field Memory", IEEE Transactions on Consumer Electronics, vol. 34, No. 3, Aug. 1988, pp. 397-401.
Morris, S. Brent et al., "Processes for Random and Sequential Accessing in Dynamic Memories", IEEE Transactions on Computers, vol. C-28, No. 3, Mar. 1979, pp. 225-237.
Motorola, :16Kx4 Bit Synchronous Statis RAM with Output Registers and Output Enable, Motorola Semiconductor Technical Data, MCM6293.
Motorola, "16Kx4 Bit Synchronous Statis RAM with Output Registers and Output Enable", Motorola Semiconductor Technical Data, MCM6294.
Nakagawa et al., "A 1Mb Field Memory For TV Pictures", IEEE 1987 Custom Integrated circuits Conference, pp. 319-322.
Ohara, Kazuhiro et al., "A Field Store System with Single 1-Mbit Field Memory, ICCE Digest of Technical Papers", pp. 70-71, Jun., 1988.
Wada, R. et al., "A Color Television Receiver With Digital Frame Memory", 1966 IEEE Transactions on Consumer Electronics, vol. 4, No. 3, pages 128-129.
Hawley, David, "Superfast Bus Supports Sophisticated Transactions," High Performance Systems, Sep. 1989.
T. Yang, M. Horowitz, B. Wooley, "A 4-ns 4KX1-bit Two-Port BiCMOS SRAM," IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1030-1040 (Oct. 1988).
"Burndy Connects Advertisement," Electronic Engineering Times, pp. T24-T25 (Feb. 24, 1986).
A. Kahn, "What's the Best Way to Minimize Memory Traffic," High Performance Systems, pp. 59-67 (Sep. 1989).
N. Margulis, "Single Chip RISC CPU Eases System Design." High Performance Systems, pp. 34-36, 40-41, 44 (Sep. 1989).
R. Matick, "Comparison of Memory Chip Organizations vs. Realiability in Virtual Memories," FTCS 12th Annual International Symposium Fault-Tolerant Commiting, IEEE Computer Society Fault-Tolerant Technical Committee, pp. 223-227 (Jun. 22, 1982).
Agarwal et al. "Scaleable Director Schemes for Cache Consistency, " 15th Intern. Sump. Comp. Architecture, pp. 280-289 (Jun. 1988).
Agarwal et al., "An Analytical Cache Model," ACM Trans. on Computer Systems, vol. 7 No. 2, pp. 184-215 (May 1989).
Davidson, "Electrical Design of a High Speed Computer Package", IBM J. Res. Develop., vol. 26, No. 3, pp. 349-361 (1982).
Hart, "Multiple Chips Speed CPU Subsystems", High-Performance Systems, pp. 26-55 (Sep. 1989).
Beresford, "How to Tame High Speed Design", High-Performance Systems, pp. 78-83 (Sep. 1989).
Carson, "Advance On-Focal Plane Signal Processing for Non-Planar Infared Mosaics," SPIE, vol. 311, pp. 53-58 (1981).
Horowitz et al., "MIPS-X: A 20-MIPS Peak 32-Bit Mocroprocessor with ON-Chip Cache," IEEE J. Solid State Circuits, vol. SC-22, No. 5, pp. 790-799 (Oct. 1987).
Kwon et al., "Memory Chip Organizations for Improved Reliability in Virtual Memories," IBM Technical Disclosure Bulletin, vol. 25, No. 6, Nov. 1982, pp. 2952-2957.
Pease et al., "Physical Limits to the Useful Packaging Density of Electronic Systems," IBM J. Res. Develop. vol. 32 No. 5, (Sep., 1988).
Peterson, "System-Level Concerns Set Performance Gains," High-Performance Systems, pp. 71-77 (Sep. 1989).
Wooley et al., "Active Substrate System Integration," Private Communication, Semiconductor Research Corporation, 4 pages (Mar. 15, 1988
Dolait Jean-Pierre
Frantz Gene A.
Hashimoto Masashi
Moravec John Victor
Bassuk Lawrence J.
Donaldson Richard L.
Popek Joseph A.
Texas Instruments Incorporated
LandOfFree
Memory circuit accommodating both serial and random access, havi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory circuit accommodating both serial and random access, havi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit accommodating both serial and random access, havi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1289795