Memory circuit

Details Memory circuit Memory circuit

2000-02-02

2001-12-11

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S189040, C365S243000

Reexamination Certificate

active

06330204

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory circuit having a fuse for use in circuit trimming, one-time ROM (Read Only Memory).
2. Description of the Prior Arts
Conventionally, a memory circuit having a fuse of polysilicon or the like in the semiconductor circuit stores data having a 1/0 value depending upon the presence or absence of disconnection in the fuse. A memory circuit of this kind is one type of programmable PROM which allows a user to freely write data thereon after manufacture, and constitutes a read only memory.
FIG. 5
shows a circuit configuration of a first conventional memory circuit as stated above. In the figure, a fuse
1
forming part of a semiconductor circuit is formed of polysilicon. The fuse
1
has one end connected to an external power supply so that an external voltage Vpp (12V-20V) is applied thereto. The fuse
1
is blown out due to Joule heat produced when a certain current or greater flows through. The fuse
1
in a blown state stores data “0” while it in an unblown state stores data “1”.
An N-channel MOS (Metal Oxide Semiconductor) transistor
2
serves as a switch element that decides whether to flow current though the fuse
1
or not. The N-channel MOS transistor
2
has a drain terminal connected through the fuse
1
to the external power supply (not shown) and a source terminal that is grounded. Also, the N-channel MOS transistor
2
is on/off-controlled by a disconnect (write) signal SW inputted to its gate terminal.
A sense line
3
connects between the other end of the fuse
1
(N-channel MOS transistor
2
drain terminal) and a read-out circuit
5
. Another N-channel MOS transistor
4
is inserted on the sense line
3
to have its drain terminal connected to a side of the fuse
1
and its source terminal connected to a side of the read-out circuit
5
. The N-channel MOS transistor
4
is to be on/off-controlled by a read signal SR inputted to the gate terminal.
The read-out circuit
5
compares a voltage on the sense line
3
with a reference voltage to read out a state of the fuse
1
(storage data) and output it as read-out data D. Specifically, the read-out circuit
5
outputs read-out data D “1” when the voltage on the sense line
3
is higher than the reference voltage. On the other hand, it outputs read-out data D “0” when the voltage on the sense line
3
is equal to or lower than the reference voltage.
In the above configuration, where storing data “0” on the memory circuit of
FIG. 5
, a not-shown control circuit outputs a disconnect signal SW to the gate terminal of the N-channel MOS transistor
2
. This causes the N-channel MOS transistor
2
to turn on so that an external voltage Vpp supplied for each power voltage Vcc is applied to the fuse
1
. If at this time the external voltage Vpp is raised to as high as 12V-20V, then a current flows through the fuse
1
. As a result, the fuse
1
is blown out due to occurrence of Joule heat. Accordingly, the fuse
1
in this case serves as a memory element storing data “0”.
to read out the data “0” stored by the fuse
1
, the control circuit (not shown) outputs a read signal SR to the gate terminal of the N-channel MOS transistor
4
. This turns on the N-channel MOS transistor
4
. In this case, however, the fuse
1
is blown so that the external voltage Vpp is not being applied on the sense line
3
. Due to this, in the read-out circuit
5
the voltage on the sense line
3
is not greater than the reference voltages. Thus, the read-out circuit
5
outputs dead-out data D “0”.
On the other hand, in a state the fuse
1
is not blown or data “1” is stored on the fuse
1
, when a read signal SR is inputted from the control circuit (not shown) to the gate terminal of the N-channel MOS transistor
4
, the N-channel MOS transistor
4
tuns on. The fuse
1
in this case is not blown. Consequently, the voltage on the sense line
3
is pulled up so that in the read-out circuit
5
the voltage on the sense line
3
is higher than the reference voltage. Thus, the read-out circuit
5
outputs read-out data D “1”. At this time the external voltage Vpp is nearly at the same as the power supply voltage Vcc so as not to flow an excessively great voltage through the fuse.
FIG. 6
shows a circuit configuration of a second conventional memory circuit. In this figure, the corresponding parts to those of
FIG. 5
are denoted by the same reference numerals, and duplicative explanations thereof are omitted. In
FIG. 6
, there is not provided the N-channel MOS transistor
2
shown in
FIG. 5
, wherein a bias voltage Vcc, e.g. power supply voltage Vcc, in place of the external voltage Vpp is applied to the fuse
1
. This bias voltage Vcc is a voltage to be applied to various parts of the memory circuit. Meanwhile, the fuse
1
is to be flown out due to the laser light L radiated from a not-shown laser oscillator.
In the above configuration, where storing data “0” in the memory circuit of
FIG. 6
, the not-shown laser oscillator radiates laser light L onto the fuse
1
. This blows out the fuse
1
due to heat produced by the laser light L. Therefore, the fuse
1
in this case serves as a memory element to store data “0”.
Where reading out data “0” stored on the fuse
1
, if a read signal SR is outputted from the control circuit (not shown) to the gate terminal of the N-channel MOS transistor
4
, the N-channel MOS transistor
4
turns on. In this case, however, because the fuse
1
is in blown, the sense line
3
is in a state that no bias voltage Vcc is applied thereto. Thus, read-out data D “0” is outputted from the read-out circuit
5
.
On the other hand, if a read signal SR is inputted from the control circuit (not shown) to the gate terminal of the N-channel MOS transistor
4
in the state that the fuse
1
is not in a blown state, or in a state “1” data is stored on the fuse
1
, then the N-channel MOS transistor
4
turns on. In this case, the voltage on the sense line
3
is pulled up because the fuse
1
is not in blown. Accordingly, read-out data D “1” is outputted from the read-out circuit
5
.
The conventional memory circuit of
FIG. 5
, however, uses two systems of power supplies including a power supply for biasing and an external power supply for blowing the fuse
1
out. This results in a problem that the conventional memory circuit is complicated in circuit configuration because of using two power supply systems.
On the other hand, the conventional memory circuit of
FIG. 6
radiates laser light L to the fuse
1
thereby performing data writing. However, such write operation is possible only before mounting the memory circuit in a package (not shown). That is, the conventional memory circuits have an disadvantage that data writing is impossible to perform after mounting the memory circuit in a package resulting in poor usability.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a memory circuit which is capable of writing data with a simplified configuration and hence being improved in usability.
In accordance with the present invention, a memory circuit formed on a semiconductor substrate, comprises: a fuse having one end connected to a power supply potential to have a disconnect/connect state storing data
0
/
1
; a switching element inserted between the other end of the fuse and a ground; a read-out circuit for reading out data stored on the fuse; a drive control means for driving and controlling the switching element when writing to the fuse.
With this configuration, where data
1
is to be stored on the fuse the drive control means does not drive the switching element. Consequently, no current flows through the fuse so that the fuse not blown out stores data
1
. This allows the data
1
to be read out of the read-out circuit.
Meanwhile, where data
0
is to be stored on the fuse, the switching element is driven by the drive control means. This connects the internal power supply to the ground through the fuse and switching element. The fuse is blown out by a large current flowing through it, being stored w

Affiliated with

Also associated with

Rating

Memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2556113