Memory circuit

Details Memory circuit Memory circuit

1997-04-29

1998-06-09

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Multiple port access

365149, 365150, 365 72, G11C 506

Patent

active

057645884

ABSTRACT:
A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n.gtoreq.2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2.sup.n-1. This results in decreasing the number of bit lines and the area of the memory.

REFERENCES:
patent: 4322824 (1982-03-01), Allan
patent: 5276650 (1994-01-01), Kubota
patent: 5584874 (1996-12-01), Doluca
patent: 5644532 (1997-07-01), Chqng

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