Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-05-30
2003-10-28
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S189070
Reexamination Certificate
active
06639856
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the memory technology field. More specifically, the invention relates to a memory chip having memory cells and an address circuit which is connected to address lines for the purpose of supplying an address. The address circuit is connected to the memory cells via selection lines for the purpose of activating the memory cells. Following presentation of an address on the address lines, the address circuit activates a prescribed memory cell via the selection lines, so that a data item can be read from the memory cell or can be written to the memory cell. The address circuit is connected to standby memory cells via further selection lines. A first address memory is provided which can store addresses for faulty memory cells. The address circuit compares a prescribed address with the addresses in the first address memory and, if the prescribed address is held in the first address memory, activates a standby memory cell instead of the faulty memory cell.
The invention further pertains to a method for checking memory cells of a repaired memory chip. In the generic method, a memory cell is stipulated by the presentation of an address, and the memory cell associated with the address is activated for the purpose of writing or reading a data item. A repair procedure for a memory cell identified as being faulty stipulates a standby memory cell which, upon presentation of the address of the faulty memory cell, is activated instead of the faulty memory cell.
Memory chips have a multiplicity of memory cells which are produced using a multiplicity of complex procedural steps. For the memory cells to operate correctly, great demands need to be placed on the quality of the procedural steps. The great demands and the multiplicity of memory cells mean that it is scarcely possible for all the memory cells to be operable following production of the memory chip. However, since it is not economical to reject the entire memory chip on account of single faulty memory cells, a test procedure is performed following production of the memory chip, wherein the operability of the memory cells is checked. If faulty memory cells are identified, the memory chip contains standby memory cells, and a faulty memory cell is replaced by a standby memory cell. To this end, the address of the faulty memory cell is assigned the standby memory cell in an address circuit. Redirection from the faulty memory cell to the standby memory cell allows the memory chip to be used following repair without adversely affecting the performance of the memory chip. A corresponding memory chip is described in U.S. Pat. No. 5,894,441.
Despite the described method for repairing faulty memory cells, faulty memory cells can be present again after the repair has been carried out.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory chip and a method for checking memory cells of a memory chip, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows an improved account to be given of the operability of the memory cells of the memory chip.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory chip, comprising:
a plurality of memory cells;
an address circuit connected to address lines for supplying an address and to the memory cells via selection lines for activating respective the memory cells;
the address circuit, upon receiving an address on the address lines, activating a prescribed memory cell via the selection lines, to enable a data item to be read from or to be written to the memory cell;
standby memory cells connected to the address circuit via further selection lines;
a first address memory connected to the address circuit for storing addresses for faulty memory cells;
the address circuit comparing a prescribed address with the addresses in the first address memory and, if the prescribed address is held in the first address memory, activating a respective the standby memory cell instead of the faulty memory cell;
a test circuit connected to the address circuit, and outputting a signal to the address circuit in a test mode; and
if the signal is present and an address for a faulty memory cell is applied, the address circuit activating the faulty memory cell instead of the respective the standby memory cell.
One advantage of novel memory chip is that, following the performance of a repair wherein faulty memory cells have been replaced by standby memory cells, the memory chip can be switched back to the original state, i.e. to the state before the repair. This makes it possible to carry out a further check on the operability of the memory cells following the repair, but using the faulty memory cells. It is thus possible, by way of example, to spot whether a faulty memory cell has been overlooked, or whether the repair itself has produced a fault in the memory chip and hence the operability of a memory cell has been impaired. A time saving and an increase in quality can thus be achieved, particularly when verifying new circuit designs. On the basis of the test result, it is also possible to check test functions which are used for checking the memory cells. This also permits a time saving and an increase in quality when developing and checking test functions.
In accordance with an added feature of the invention, there are provided an address circuit and a standby address circuit. The standby address circuit is connected to a test circuit. The standby address circuit receives the test signal from the test circuit, and the standby address circuit prevents a faulty memory cell from being addressed by a standby memory cell when the test signal is present. This returns the memory chip to the unrepaired state.
Preferably, storage of the address of the faulty memory cell is designed to be in the form of fuses. The use of fuse technology affords a simple and fully matured technology for storing the addresses.
In accordance with a preferred refinement of the invention, the test circuit is formed using two series-connected transistors and a latch memory connected between the transistors. The two transistors are switched by a control generator, with the latch memory being set to a default value or to a voltage value stipulated by a fuse, depending on the switching state of the two transistors. This permits a simple design for the test circuit.
With the above and other objects in view there is also provided, in accordance with the invention, a method of checking memory cells of a repaired memory chip, where a memory cell is stipulated by the presentation of an address, and the memory cell associated with the address is activated for writing or reading a data item, where a repair procedure for a memory cell identified as being faulty stipulates a standby memory cell which, upon presentation of the address of the faulty memory cell, is activated instead of the faulty memory cell. The method is characterized by a step of activating the faulty memory cell instead of the standby memory cell when a test signal has been presented.
An advantage of the inventive method as outlined above is that even in a repaired memory chip, for which a standby memory cell is activated at an address for a faulty memory cell, the memory cell identified as being faulty is activated again for a checking procedure instead of the standby memory cell. This allows the memory cell identified as being faulty to be tested. It is thus possible to improve test procedures and, by way of example, to compare the test response of the memory chip before repair with the test response of the memory chip after repair. Faults caused by the repair operation are thus identified, for example.
In accordance with a concomitant feature of the invention, the repair of a memory cell identified as being faulty by a redundant memory cell is reversed if the test procedure shows that the memory cell identified as being faulty is actually operating correctly.
Other features whi
Beer Peter
Ohlhoff Carsten
Greenberg Laurence A.
Infineon - Technologies AG
Lam David
Locher Ralph E.
Stemer Werner H.
LandOfFree
Memory chip having a test mode and method for checking... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory chip having a test mode and method for checking..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory chip having a test mode and method for checking... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3169382