Memory chip for high capacity memory subsystem supporting...

Details Memory chip for high capacity memory subsystem supporting... Memory chip for high capacity memory subsystem supporting...

2007-06-27

2010-10-26

Thai, Tuan V (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

07822936

ABSTRACT:
A memory module contains a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.

REFERENCES:
patent: 5893927 (1999-04-01), Hovis
patent: 6502161 (2002-12-01), Perego et al.
patent: 7120727 (2006-10-01), Lee et al.
patent: 7136958 (2006-11-01), Jeddeloh
patent: 7378868 (2008-05-01), Tyhach et al.
patent: 7397684 (2008-07-01), Ruckerbauer et al.
patent: 7411843 (2008-08-01), Ruckerbauer et al.
patent: 7477717 (2009-01-01), Kuzmenka et al.
patent: 2002/0023191 (2002-02-01), Fudeyasu
patent: 2002/0084458 (2002-07-01), Halbert et al.
patent: 2004/0243769 (2004-12-01), Frame et al.
patent: 2004/0256638 (2004-12-01), Perego et al.
patent: 2005/0144403 (2005-06-01), Jeddeloh
patent: 2005/0210216 (2005-09-01), Jobs et al.
patent: 2006/0245226 (2006-11-01), Stewart
patent: 2006/0265533 (2006-11-01), Hobson et al.
patent: 2007/0079057 (2007-04-01), Ruckerbauer et al.
patent: 2007/0124532 (2007-05-01), Bennett
patent: 2008/0077732 (2008-03-01), Risse
patent: 2008/0250270 (2008-10-01), Bennett
patent: 1628225 (2006-02-01), None
U.S. Appl. No. 11/459,956, filed Jul. 26, 2006, “Daisy Chained Memory System”.
U.S. Appl. No. 11/459,957, filed Jul. 26, 2006, Memory System Having Self Timed Daisy Chained Memory Chips.
U.S. Appl. No. 11/459,969, filed Jul. 26, 2006, “Carrier Having Daisy Chained Memory Chips”.
U.S. Appl. No. 11/459,983, filed Jul. 26, 2006, “Carrier Having Daisy Chain of Self Timed Memory Chips”.
U.S. Appl. No. 11/459,994, filed Jul. 26, 2006, “Daisy Chainable Memory Chip”.
U.S. Appl. No. 11/459,997, filed Jul. 26, 2006, “Daisy Chainable Self Timed Memory Chip”.
U.S. Appl. No. 11/459,974, filed Jul. 26, 2006, “Computer System Having Daisy Chained Memory Chips”.
U.S. Appl. No. 11/459,968, filed Jul. 26, 2006, Computer System Having Daisy Chained Self Timed Memory Chips.
U.S. Appl. No. 11/459,966, filed Jul. 26, 2006, “Memory Controller for Daisy Chained Memory Chips”.
U.S. Appl. No. 11/459,961, filed Jul. 26, 2006, “Memory controller for Daisy Chained Self Timed Memory Chips”.
U.S. Appl. No. 11/459,943, filed Jul. 26, 2006, “Memory Chip Having an Apportionable Data Bus”.
U.S. Appl. No. 11/459,947, filed Jul. 26, 2006, “Self Timed Memory Chip Having an Apportionable Data Bus”.
U.S. Appl. No. 11/459,955, filed Jul. 26, 2006, “Computer System Having an Apportionable Data Bus”.
U.S. Appl. No. 11/459,959, filed Jul. 26, 2006, “Memory System Having an Apportionable Data Bus and Daisy Chained Memory Chips”.

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