Memory chip array with inverting and non-inverting address drive

Details Memory chip array with inverting and non-inverting address drive Memory chip array with inverting and non-inverting address drive

1986-10-14

1989-09-26

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365 63, 365214, G11C 702

Patent

active

048706191

ABSTRACT:
A memory arrangement is comprised of a plurality of memory chips, and address and control lines connected to the chips. In order to minimize the effect of interference of signals from the address lines on the control lines, the address lines coupled to a portion of the chips carry address signals in inverted form, as compared with the address signals applied to the remainder of the chips, whereby interference signals of opposite polarity are induced in the control lines and cancel each other.

REFERENCES:
patent: 3161860 (1964-12-01), Grooteboer
patent: 4596001 (1986-06-01), Baba

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