Memory chip and apparatus for testing a memory chip

Details Memory chip and apparatus for testing a memory chip Memory chip and apparatus for testing a memory chip

2005-11-01

2005-11-01

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06961882

ABSTRACT:
The present invention provides a memory chip (100) which can be operated in a normal mode and in a test mode (TM) and which has a device (102) for outputting data from the memory chip (100) and a device (104) for enabling the device (102) for outputting data when the test mode (TM) has been activated. The device (104) for enabling the device (102) for outputting data has a device for masking data so that only particular portions of the data are output when a data masking state (DQM) has been activated.

REFERENCES:
patent: 5619461 (1997-04-01), Roohparvar
patent: 5875137 (1999-02-01), Suzuki
patent: 6480432 (2002-11-01), Nakayama
patent: 2001/0013110 (2001-08-01), Pierce et al.

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