Memory channel self test

Details Memory channel self test Memory channel self test

2008-01-22

2008-01-22

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S724000

Reexamination Certificate

active

07321997

ABSTRACT:
A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory module, while further employing another buffer logic that is interposed between the two memory modules to pass on the test pattern, but intercept a signal received from the other memory module during the test and pass on an indication of the receipt of that signal to an analysis device to monitor the test.

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patent: 6502161 (2002-12-01), Perego et al.
patent: 6771087 (2004-08-01), Oz et al.
patent: 2002/0056062 (2002-05-01), Hartmann
patent: 2002/0125879 (2002-09-01), Lee et al.
patent: 2003/0041086 (2003-02-01), Lankreijer

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