Memory cells with lower power consumption during a write...

Details Memory cells with lower power consumption during a write... Memory cells with lower power consumption during a write...

2006-12-27

2009-10-27

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S226000, C365S189040

Reexamination Certificate

active

07609541

ABSTRACT:
A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.

REFERENCES:
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patent: 6205049 (2001-03-01), Lien et al.
patent: 6459611 (2002-10-01), Rimondi
patent: 6903962 (2005-06-01), Nii
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patent: 2005/0162919 (2005-07-01), Nii
patent: 2006/0250880 (2006-11-01), Ramaraju et al.
patent: 2007/0139997 (2007-06-01), Suzuki et al.
Hiep Tran, Demonstration of 5T SRAM And 6T Dual-Port RAM Cell Arrays, IEEE 1996, pp. 68-69.

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