Memory cells, memory devices and integrated circuits...

Static information storage and retrieval – Systems using particular element – Semiconductive

Reexamination Certificate

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C365S159000, C365S174000, C365S175000, C365S181000

Reexamination Certificate

active

07630235

ABSTRACT:
A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.

REFERENCES:
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patent: 2007/0096203 (2007-05-01), Mouli
Nemati, Farid et al., “Fully Planar 0.562μm2 T-RAM Cell in a 130 nm SOI CMOS Logic Technology for High-Density High Performance SRAMs,” IEEE, ISBN: 0-7803-8684-1, pp. 273-276, Dec. 2004.
Cho, Hyun-Jin et al., “A Novel Capacitor-less DRAM Cell using Thin Capacitively-Coupled Thyristor (TCCT),” IEEE, ISBN: 0-7803-9268-x, pp. 311-314, Dec. 2005.
International Search Report for PCT/US2008/003362, mailed Jul. 2, 2008.

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