Memory cells enhanced for resistance to single event upset

Details Memory cells enhanced for resistance to single event upset Memory cells enhanced for resistance to single event upset

2005-07-05

2005-07-05

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S072000, C365S148000, C365S155000, C365S156000

Reexamination Certificate

active

06914804

ABSTRACT:
Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

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