Memory cells configurable as CAM or RAM in programmable...

Details Memory cells configurable as CAM or RAM in programmable... Memory cells configurable as CAM or RAM in programmable...

2000-03-10

2001-07-17

Verbrugge, Kevin (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S049130

Reexamination Certificate

active

06263400

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
In one aspect, the present invention relates generally to programmable logic devices that incorporate reconfigurable dual mode memory. In another aspect, reconfigurable dual mode memory that is arranged to function as either CAM or RAM is described.
2. Description of the Related Art
A programmable logic device or PLD is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. The logic functions previously performed by small, medium, and large scale integration integrated circuits can instead be performed by programmable logic devices. When a typical programmable logic device is supplied by an integrated circuit manufacturer, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform the specific function or functions required by the user's application. The PLD then can function in a larger system designed by the user just as though dedicated logic chips were employed. For the purpose of this description, it is to be understood that a programmable logic device refers to once programmable as well as reprogrammable devices.
Programmable logic encompasses all digital logic circuits configured by the end user, including field programmable gate arrays (FPGAs) and complex PLDs (CPLDs). An example of a CPLD is known as the embedded array programmable logic device. Embedded array programmable logic devices utilize a plurality of embedded array blocks, or EABs, programmably interconnected to form a memory and logic array to implement memory and specialized logic functions. General logic functions are implemented by use of a logic array consisting of programmably interconnected logic array blocks, or LABs. By suitably programmably interconnecting the array of EABs and the array of LABs, an embedded array programmable logic device is capable of implementing many complex logic and combined logic/memory functions.
The embedded array programmable logic device architecture may be formed by a plurality of logic array blocks arranged in rows and columns coupled by way of programmable connectors to a plurality of horizontal and vertical conductors. In a similar manner, an array of embedded array blocks may be arranged such that at least one EAB is present in every row of logic array blocks. The array of EABs are also coupled to the plurality of horizontal and vertical conductors by way of a plurality of programmable connectors. By way of example,
FIG. 1
is an illustration of an embedded array programmable logic device architecture as exemplified by the FLEX10K™ logic family of devices manufactured by the Altera Corporation of San Jose, California. As described above, logic array blocks
104
a
and
104
b
are arranged to form a portion of a row
150
which contains a single embedded array block
102
a
. A second row
152
is formed in a substantially similar manner, a portion of which includes the arrangement of logic array blocks
104
c
and
104
d
and embedded array block
102
b.
As described above, each LAB and EAB may be programmably coupled to the plurality of vertical and horizontal conductors by appropriately situated programmable connectors. As an example, LAB
104
a
included in a portion of row
150
may be electrically coupled to a first plurality of horizontal conductors
174
and a second plurality of horizontal conductors
176
by programmable connectors
180
and
182
, respectively. In a similar fashion, LAB
104
a
may be electrically coupled to a first plurality of vertical conductors
190
and a second plurality of vertical conductors
192
by programmable connectors
194
and
196
, respectively. In a similar fashion each of the array of EABs may be electrically coupled to at least one of each of the plurality of vertical and horizontal conductors. By way of example, EAB
102
a
may be electrically coupled to vertical conductors
192
and
191
by way of programmable connectors
195
and
197
, respectively, and horizontal conductors
174
and
176
by way of programmable connectors
193
and
199
, respectively. In this way, an embedded array programmable logic device capable of implementing many complex logic and combined logic/memory functions is formed.
The EAB is a flexible block of random access memory, or RAM, with registers on the input and output ports. As is known in the art, a RAM is an array of individual memory cells, of which each cell includes a plurality of transistors configured to store digital data in the form of a single bit. Typically, the individual memory cells are arranged to form data words of varying length depending upon the particular application. In practice, data words may be of any length, however, data word lengths of 1, 8, 16, or 32 bits are common but any word length desired by the user is possible. As structured, the RAM device has the ability to access, or read, each stored data bit or data word independently of any other stored data bit or word by selectively enabling desired rows and columns.
Many applications such as database machines, image or voice recognition, or computer and communication networks require high speed searches of data bases, lists, or patterns. Commonly, high speed searches using RAM employ search algorithms such as binary, tree-based searches, or look aside tag buffers. Unfortunately, the structure of the RAM requires these algorithms to sequentially compare the desired information against the pre-stored data within the RAM in a manner that is relatively slow, thereby leading to unacceptable search times.
To address the need for high speed searches in large data bases, lists or patterns, a device known in the art as the content addressable memory, or CAM, was developed. The CAM is a memory device that accelerates the applications such as database machines, image or voice recognition, or computer and communications networks that require fast searches of a data base, list, or pattern. CAMs may have significant performance advantages over use of RAM in performing high speed searches of databases, lists, and patterns since CAMs compare the entire list of prestored data simultaneously. Typically, in performing high speed searches, the CAM based search engine delivers up to an order of magnitude faster performance than a RAM based search engine.
In view of the foregoing, it would be advantageous and therefore desirable to provide a programmable logic device having an efficient configurable content addressable memory cell.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a programmable logic device having content addressable memory is disclosed. In a preferred embodiment, reconfigurable dual mode memory suitable for operating as a content addressable memory in a first mode and a random access memory in a second mode is disclosed. Mode control switch circuitry may be provided to selectively enable a user to configure the dual mode memory as either content addressable memory or random access memory.
In one preferred embodiment, the dual mode memory block includes a multiplicity of dual mode memory cells having a plurality of columns and rows suitably arranged to outputting match addresses corresponding to requested data words when the dual mode memory block is configured to operate as content addressable memory.
The dual mode memory cells may also include a plurality of dual mode memory cell data lines, a row line, a match line, a data storage circuit for storing data, a comparison circuit for comparing the stored data with requested data, and an isolation circuit for selectably isolating the data storage circuit and the comparison circuit.
The programmable logic device may also include a comparand unit for storing and queuing requested data and a priority encoder. The priority encoder being suitable for receiving and storing match addresses as

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