Memory cell with vertical transistor and trench capacitor

Details Memory cell with vertical transistor and trench capacitor Memory cell with vertical transistor and trench capacitor

2002-11-18

2004-02-24

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000, C257S304000, C257S306000, C257S328000

Reexamination Certificate

active

06696717

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor device. More particularly, it relates to a memory cell with a vertical transistor and a trench capacitor that enhances electrical properties and increases integration with integrated circuits (ICs).
2. Description of the Related Art
With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are produced based on different objectives. The dynamic random access memory (DRAM) is such an important semiconductor device in the information and electronics industry. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells.
Most DRAMs have one transistor and one capacitor in one DRAM cell. The memory capacity of the DRAM has reached 256 megabits. Therefore, under increasing integration it is required to shrink the size of the memory cell and the transistor so as to manufacture the DRAM with higher memory capacity and higher processing speed. A 3-D capacitor structure can itself reduce occupied area in the semiconductor substrate, so the 3-D capacitor, such as a deep trench capacitor, is applied to the fabrication of the DRAM of 64 megabits and above. Traditional DRAM with a plane transistor covers larger areas of the semiconductor substrate and cannot satisfy the demand of high integration. Therefore, a vertical transistor which can save space is a trend in fabrication of a memory cell.
There is much interest in reducing the size of individual semiconductor devices to increase their density on an IC chip. This reduces size and power consumption of the chip, and allows faster operation. In order to achieve a memory cell with minimum size, the gate length (line width) in a conventional plane transistor must be reduced to decrease the lateral dimension of the memory cell. However, punch through, drain-induced barrier lowering (DIBL), and threshold voltage roll-off occur when the line width is shrink, as known to those of ordinary skill in the art. In order to solve those problems, heavy doping areas are formed in the substrate between drain and source of the plane transistor by halo implantation, thereby preventing punch trough and DIBL and raising the threshold voltage. Unfortunately, in a vertical transistor structure, it is difficult to perform halo implantation. Since the vertical transistor is a trend in fabrication of a memory cell, another way to prevent punch through, DIBL, and threshold voltage roll-off is needed.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a novel memory cell with a vertical transistor and a trench capacitor, in which the gate material of the vertical transistor is composed of two kinds of materials having different work function, thereby changing its channel property from halo implantation for conventional plane transistor.
According to one aspect, the invention provides a memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate, a trench capacitor, a control gate, a first insulating layer, a first doped region, and a second doped region. The substrate has a trench. In the lower trench, there is a trench capacitor disposed, which has a bottom electrode formed in the substrate around the low trench. The control gate, which has a first conductive layer and an overlying second conductive layer, is disposed in the upper trench and insulated from the substrate. The first insulating layer is disposed between trench capacitor and the control gate. The first doped region is formed in the substrate around the first insulating layer and the second doped region is formed in the substrate around the second conductive layer.
Moreover, the memory cell further includes a third conductive layer, which is disposed between the first insulating layer and the trench capacitor, and an interfacial layer, which is disposed between the third conductive layer and the first doped region. The first conductive layer is p-type polysilicon germanium and the second conductive layer is p-type polysilicon.


REFERENCES:
patent: 6566177 (2003-05-01), Radens et al.
patent: 2002/0085434 (2002-07-01), Mandelman et al.

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