Memory cell with vertical transistor and trench capacitor...

Details Memory cell with vertical transistor and trench capacitor... Memory cell with vertical transistor and trench capacitor...

2002-09-30

2004-07-06

Faboring, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000

Reexamination Certificate

active

06759702

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor memory structures and, more particularly, to memory structures having vertical transistors and trench capacitors with buried straps.
BACKGROUND OF THE INVENTION
Semiconductor memory structures including vertical transistors and trench capacitors with buried straps along all side walls or only one side wall of a deep trench (DT) are known. See, for example, U.S. Pat. Nos. 6,288,422; 6,339,241; and U.S. Pat. No. 6,426,526, entitled “Single Sided Buried Strap,” by Divakaruni et al., filed May 30, 2001, which are all incorporated in their entireties herein by reference. See also the publications: U. Gruening et al., “A Novel Trench DRAM Cell with a VERtIcal Access Transistor and BuriEd Strap (VERI BEST) for 4 Gb/16 Gb,” 1999 IEEE,
IEDM
99-25, pps. 2.1.1 to 2.1.4; C. J. Radens et al., “An Orthogonal 6F
2
Trench-Sidewall Vertical Device Cell for 4 Gb/16 Gb DRAM,”
Proceedings of IEDM
, San Francisco, Calif., Dec. 10-13, 2000, pps. 15.1.1 to 15.1.4; and T. Rupp et al., “Extending Trench DRAM Technology to 0.15 &mgr;m Groundrule and Beyond”, 1999 IEEE,
IEDM
99-33, pps. 2.3.1 to 2.3.4, which all are also, incorporated in their entireties herein by reference.
In a figure of the '241 patent, as reproduced in
FIG. 13
herein, there is shown a cross-sectional view of an embodiment of a known memory cell structure of a type to which the present invention relates. From the '241 patent,
FIG. 15
further clarifies FIG.
13
.
FIG. 14
also clarifies FIG.
13
. The memory cell structure
20
illustrated in
FIG. 13
, FIG.
14
and
FIG. 15
is formed in a known manner in a semiconductor substrate. A buried N plate
22
is arranged in the substrate. Deep trenches
24
,
26
are formed in the substrate into the buried N plate.
Collar oxide
28
is formed on a sidewall of each deep trench. The collar oxide
28
may extend about the entire deep trench in certain regions of the deep trench as indicated by collar oxide portions
30
. Node dielectric
32
is provided on portions of the deep trench walls and collar oxide regions
30
. The bottom portion of the trench is filled with N+ doped polysilicon
34
.
On top of this region of polysilicon lies trench top oxide region
36
. Buried strap
37
is arranged as shown in
FIG. 13 and 14
, between the collar oxide region
36
and the trench top oxide
36
. The strap
37
includes doped polysilicon. A buried strap out diffusion
38
lies adjacent to the trench top oxide region and part of the collar oxide region
30
. The strap (heavy line
37
of
FIG. 15
) extends along a distance of the perimeter of the deep trench
26
, the distance being approximately 25% (i.e., approx. one lithographic feature size F) of the entire trench
26
perimeter P lying in a plane parallel to the plane of FIG.
1
. The plane in which the trench perimeter P lies is also normal to the depth direction of the trench
26
.
Portions of the deep trench above the trench top oxide region
36
are also filled with N+ doped polysilicon
40
, which serves as a gate conductor. Gate oxide
42
is provided between the N+ doped polysilicon
40
region and the wall of the deep trench.
P-type channel doping profile (VA/P) regions
44
for the channel of the vertical MOSFET lie adjacent to the portion of the deep trench down to the level of the bottom of the N+ doped polysilicon regions
40
. N+(XA/N+) regions
46
, which define the bitline contact diffusion, lie above VA/P regions
44
adjacent to the deep trench regions illustrated in
FIG. 13
, while XA region
48
lies above the VA/P region
44
between the two deep trenches
24
,
26
in the embodiment illustrated in FIG.
13
.
Tungsten and silicon regions
52
overlie the top of the deep trenches
24
,
26
. On top of and adjacent to sides of the tungsten and polysilicon regions
52
lie Si
3
N
4
regions
54
. Nitride liner
56
merges into nitride spacer/sidewall oxide region
58
adjacent to sides of the tungsten and polysilicon and Si
3
N
4
regions
54
as well as overlying the Si
3
N
4
regions
54
.
Borophosphosilicate glass (BPSG) regions
60
overlie the nitride liner. Overying the BPSG and nitride spacer/sidewall oxide region
58
is a layer of tetraethyl ortho silicate (TEOS)
62
.
Contact-to-bitline (CB) polysilicon regions
64
, which provide a conductive stud between bitline contact diffusion XA and bitline metal MO
68
, extend out through the TEOS and BPSG layers to the level of XA regions
48
,
46
. CB TEOS liner regions
66
surround the CB polysilicon region
64
. The bitline metal/metal level 0 (MO)
68
overlies portions of the TEOS layer
62
as well as the CB polysilicon and CB TEOS liner regions
164
and
66
.
The process for forming the memory cell structure of
FIGS. 13. 14
and
15
is well known from, for example, U.S. Pat. No. 6,339,241, “Structure and Process for 6F
2
Trench Capacitor DRAM Cell with Vertical MOSFET and
3
F Bitline Pitch”, issued Jan. 15, 2002, by Mandelman et al. (hereinafter '241 patent), and need not be further discussed.
The continued scaling of advanced trench-capacitor-sidewall transistor memory (e.g., DRAM) cells is constrained by the electrical interaction between adjacent memory elements, and exacerbated by decoupling of the array well from a V
bb
supply.
An adjacent wordline disturb mechanism, and a strap-to-strap interaction mechanism, have been identified by the present inventors as scaling limitations for back-to-back trench-capacitor sidewall transistor DRAM cells sharing a single bitline diffusion in the sub-90 nm groundrule generations.
OBJECT OF THE INVENTION
The known memory cell structure such as shown in the '241 patent or in U.S. Pat. No. 6,288,422, may continue to exhibit undesirable strap-to-strap interaction can be minimized further.
Also, the process for forming the buried strap can be improved.
It is a principal object of the present invention to reduce strap-to-strap interaction over that interaction known in the prior art.
It is a further object of the present invention to confine the buried strap to a distance along the circumference of the deep trench which is substantially less than the known distance.
It is an additional object of the present invention to reduce the interaction between adjacent transistors caused by the extent of buried strap out diffusion over that known in the prior art.
It is an additional object of the present invention to improve a process for forming the buried strap.
SUMMARY OF THE INVENTION
According to the present invention, a memory cell structure includes
a semiconductor substrate,
a deep trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom,
a storage capacitor at the bottom of the deep trench,
a vertical transistor extending down a sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench,
a collar oxide extending down the sidewall of the deep trench opposite the storage capacitor,
shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends,
a gate conductor extending within the deep trench,
a wordline extending over the deep trench and connected to the gate conductor, and
a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions, and
a buried strap along the sidewall of the deep trench,
wherein the deep trench has a perimeter lying in a plane oriented in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance of the perimeter, and less than one lithographic feature size F. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The corner lies, for example, within a sector of an imaginary closed curve

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