Memory cell with trench transistor

Details Memory cell with trench transistor Memory cell with trench transistor

2001-12-18

2003-12-09

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S329000, C257S330000

Reexamination Certificate

active

06661053

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory cell with a storage transistor comprising a gate electrode at a top surface of a semiconductor body or semiconductor layer, which electrode is disposed between a source zone and a drain zone in a trench that is constructed in the semiconductor material of the semiconductor body or layer and that exhibits identical cross-sections transverse to a longitudinal direction, at least section by section, whereby a dielectric layer, preferably an ONO layer, is provided as the storage medium between the gate electrode and the semiconductor material.
2. Description of the Related Art
DE 100 39 441 A1 teaches a memory cell with a trench transistor which is disposed in a trench constructed at a top surface of a semiconductor body. Arranged between the gate electrode which is installed in the trench, the laterally adjoining source zone, and the adjoining drain zone on the other side is an oxide-nitride-oxide layer sequence, which is provided for trapping charge carriers at the source and drain. Such transistors are particularly well suited to NVM (Non-Volatile Memory) memory cell arrangements. The regions which exhibit the required electrical field intensities for programming and erasing are generally located in different positions in these transistors. As a consequence, once charges have been programmed on the nitride, it is difficult to completely erase them. An injection of electrons is required for the programming operation. The electrons must penetrate through the oxide boundary layer in order to reach the nitride layer which is provided as the storage layer. For this reason, the electrons must have a high kinetic energy, being what are known as hot electrons. Such electrons are present only where the electrical field intensity is very strong in the channel under the gate electrode at the surface of the semiconductor material.
The enclosed
FIG. 5
is a diagram representing the gate electrode
4
, the gate dielectric
9
(which can be an ONO storage layer, in particular), and the adjoining semiconductor material with the channel region
5
, from left to right. In the vertical direction, denoted by an arrow, the energy is plotted, which increases in the direction of the arrow. The plotted curves a and b indicate the upper limit of the valence band and the lower limit of the conduction band, respectively. There are two Fermi energy levels E
f1
and E
f2
. Up to these energy levels, the states, which can only be singly occupied according to the Pauli principle, are full of electrons. When the Fermi energy level E
f1
is lower, only a few electrons are located in the conduction band at the boundary of the semiconductor material, as indicated by the hatched region in FIG.
5
. It can be recognized that in the case of a higher Fermi energy level E
f2
, more electrons, and furthermore higher-energy electrons, are present in the conduction band. Therefore, for the higher-energy electrons it is easier to tunnel through the oxide layer bordering the nitride storage layer.
FIG. 6
represents a cross-section of a typical transistor structure including a source zone
2
, a drain zone
3
, a gate electrode
4
, a gate dielectric
9
and the channel region
5
. The dashed line represents the boundary of a developing space charge zone of the channel. Upon application of the provided voltages which are required for programming such a transistor, the electrons are accelerated through the channel region in the direction of the arrows. The length of the arrows (which is not true to scale) indicates the average kinetic energy of the electrons. It is clear that the average kinetic energy of the electrons increases sharply proceeding toward the drain zone
3
. This increase is extremely overproportional, because the electrical field intensity increases sharply proceeding toward the drain zone
3
until a point just before the drain zone. When the electrons reach the end of the channel region
5
, their energy is high enough that they can get into the storage layer.
In the case of a storage transistor that is disposed in a trench, the region in which the electrons have a suitable energy for programming is likewise located at the end of the channel region, which ends in this case on one side of the trench bottom directly below the junction of the p-conductive doped substrate into the n
+
-conductive doped drain region. In a cross-section with the source zone on the left and the drain zone on the right, this region of favorable programming is situated at the bottom of the trench approximately on the bottom right-hand side.
For the erase operation, an injection of holes (charge carriers with the opposite sign) are needed, which can be obtained in an n-MOSFET only by the GIDL (Gate Induced Drain Leakage) effect. This effect occurs only in the vicinity of the drain zone. The locations at which the electron injection and the hole injection occur are thus not necessarily identical. In any case, this type of memory cell can be erased with a high applied voltage and/or very long erase times.
SUMMARY OF THE INVENTION
It is the object of the present invention to construct a memory cell with a trench transistor in which the program and erase times are significantly shorter than in conventional memory cells of this type.
This object is achieved with the memory cell with the features of the independent claims. Other developments are recited in the dependent claims.
According to the invention, the depth of the trench with respect to a region in which charge carriers of the storage layer are neutralized in an erase operation is selected such that in a programming operation a component of an electrical field acting on the charge carriers, which component is aligned parallel to the tangents to a wall or to the bottom of the trench and perpendicular to the longitudinal direction of the trench, is at a maximum in the same region. This way, the trench depth is optimized in such a way that the locations for electron and hole injections coincide. The junctions in which the doping of the source zone and drain zone changes to the opposite sign, i.e. the sign of the conductivity type of the substrate or semiconductor body, abut a curved region of the trench bottom or a curved lower region of the lateral trench walls.


REFERENCES:
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patent: 196 39 026 (1998-04-01), None
patent: 100 39 441 (2002-02-01), None
patent: 0 967 654 (1999-12-01), None
patent: 4 012 573 (1992-01-01), None
patent: 98/13878 (1998-04-01), None
Junko Tanaka et al.: “A Sub-0.1-&mgr;m Grooved Gate MOSFET with High Immunity to Short-Channel Effects”,IEDM, 1993, pp. 537-540.

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