Memory cell with trench capacitor and vertical select...

Details Memory cell with trench capacitor and vertical select... Memory cell with trench capacitor and vertical select...

2007-09-11

2007-09-11

Doan, Theresa (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

10486758

ABSTRACT:
The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.

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Hyun-Jin Cho et al., “A Novel Pillar DRAM Cell for 4 Gbit and Beyond”, VLSI Technology, 1998. Digest of Technical Papers. 1998. Symposium on Honolulu, Hi, USA Jun. 9-11, 1998, New York, NY USA, IEEE, US, pp. 38-39.
K. Yamada et al., “A Deep-Trenched Capacitor Technology for 4 MEGA Bit Dynamic RAM”, UEDM 85, p. 702, 1985.

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