Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-19
2003-03-18
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06534812
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a memory cell with a stored charge on its gate, a kind of so-called DRAM gain cell.
A DRAM cell is composed of one transistor and one capacitor which can generally accomplish the minimum area among conventional RAM cells. With a design rule being finer, however, it is requested to develop a complicated capacitor structure and a new capacitor material for achieving a small area and a capacitance which a capacitor is required to have. And, the cost of DRAM production is increasing due to the formation and processing of dielectric materials and electrode films, researches and developments of passivation techniques and introduction of novel manufacturing apparatus, and the cost of the capacitor production is now much more expensive than that of the transistor production. Readout signals lessen as a finer semiconductor device is structured, and it is ultimately difficult to detect information stored in a memory cell without a change in structure and materials.
For overcoming the above problem, one DRAM gain cell is known in “Super-Low-Voltage Operation of a Semi-Static Complementary Gain DRAM Memory Cell”, S. Shukuri, et al., 1993 Symposium on VLSI Technology, Digest of Tech. Papers, 3A-4, pp 23-24, 1993.
FIG. 28
shows an equivalent circuit of the above DRAM gain cell composed of a memory transistor RM having a floating gate and a complementary word transistor WM. In the DRAM gain cell, a gate of the word transistor WM and a gate of the memory transistor RM are connected to a common word line WL, and one source/drain region of the word transistor WM and one source/drain region of the memory transistor RM are connected to a common bit line BL, so that the number of external wiring is decreased. When information is written in the above DRAM gain cell, a voltage, for example, of 1.5 volts is applied to the bit line BL, and a minus voltage is applied to the word line WL. As a result, a positive charge is stored on the floating gate of the memory transistor RM, and a gate threshold voltage of the memory transistor RM shifts toward a minus direction. When the DRAM gain cell is in a standby state, a potential is applied to the word line WL such that the memory transistor RM and the word transistor WM are not brought into an on-state. When information is read out, applied to the word line WL is a potential between the gate threshold voltage of the memory transistor RM when a positive charge is stored on the floating gate and the gate threshold voltage when no positive charge is stored. As a result, when a positive charge is stored on the floating gate, a current flows through the DRAM gain cell.
As explained above, the DRAM gain cell shown in
FIG. 28
in principle requires no capacitor although it is required as an auxiliary in some cases. However, when it is attempted to decrease the area of the DRAM gain cell, the word transistor WM is required to be composed of a thin film transistor (TFT), and the problem is that the production process is complicated and that the DRAM gain cell can be no longer produced by a conventional production process. Further, there is another problem that controllability and reproducibility of TFTs are difficult when mass production technologies available at present are applied. Moreover, there is still another problem that since the above DRAM gain cell has a small operation margin, it is required to connect the gates or the drains of the two transistors to different word lines or different bit lines for securing the operation margin, and that the area of such a DRAM gain cell cannot be decreased.
OBJECT AND SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a memory cell with a stored charge on its gate, which does not require much complicated production process, which serves to suppress an increase in the number of external wiring and the area of a terminal portion, which can be produced almost equally by applying a process of producing a conventional flash memory, which does not require complicatedly structured capacitor unlike a conventional DRAMSand which can suppress an increase in a cell area.
The memory cell with a stored charge on its gate, provided by the present invention, for achieving the above object is a memory cell comprising;
(A) a channel-forming region,
(B) a first gate formed on an insulation layer formed on the surface of the channel-forming region, the first gate and the channel-forming region facing each other through the insulation layer,
(C) a second gate capacitively coupled with the first gate,
(D) source/drain regions formed in contact with the channel-forming region, one source/drain region being spaced from the other,
(E) a first non-linear resistance element having two ends, one end being connected to the first gate, and
(F) a second non-linear resistance element composed of the first gate, the insulation layer and either the channel-forming region and at least one of the source/drain regions.
In the above first non-linear resistance element, the “one end connected to the first gate” includes a case where said one end of the first non-linear resistance element has a common region with or serves as the first gate.
In the memory cell with a stored charge on its gate, provided by the present invention (to be simply referred to as “memory cell” hereinafter), the insulation layer has a thickness which permits the flow of tunneling current in the insulation layer when a proper potential is applied between the first gate and the channel forming region or at least one of the source/drain regions which constitutes the second non-linear resistance element. The insulation layer can be formed of SiO
2
, SiN, SiON, a laminated structure of SiO
2
/SiN or the like. Of these, SiO
2
(silicon oxide layer) having a thickness of 3 nm or less is preferred for forming the insulation layer. The second non-linear resistance element preferably comprises a so-called MIS (Metal-Insulator-Semiconductor) type or MOS (Metal-Oxide-Semiconductor) type tunnel diode which is composed of the first gate, the insulation layer and the channel forming region, of the first gate, the insulation layer and one of the source/drain regions, of the first gate, the insulation layer and both of the source/drain regions; of the first gate, the insulation layer, the channel forming region and one of the source/drain regions or of the first gate, the insulation layer, the channel forming region and both of the source/drain regions.
In the memory cell of the present invention, the first non-linear resistance element preferably has a two-terminal operation characteristic. The term “two-terminal operation characteristic” refers to an operation characteristic that the amount of current which flows between two regions is uniquely determined depending upon a voltage between the two regions as in a diode.
In the memory cell of the present invention, preferably, the first non-linear resistance element has characteristics that it is brought into a low resistive state when a first voltage having the same polarity as that of a forward conduction voltage and having an absolute value which is equal to, or greater than, an absolute value of the forward conduction voltage is applied across the two ends and that it is brought into a high resistive state when a second voltage having the same polarity as that of the forward conduction voltage and having an absolute value smaller than the absolute value of the forward conduction voltage or a voltage having an opposite polarity to the forward conduction voltage is applied across the two ends. For example, when the first non-linear resistance element comprises a diode, it is preferred to use a diode having characteristics that it is brought into a low resistive state when the first voltage equal to, or higher than, the forward conduction voltage is applied.
Specifically, as the first non-linear resistance element having the above characteristics, a pn junction diode can be used. In this case, preferably, the pn junction diode
Hayashi Yutaka
Mukai Mikio
Chaudhuri Olik
Kananen, Esq. Ronald P.
Pizarro-Crespo Marcos D.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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