Memory cell with separate read and write paths and clamping tran

Details Memory cell with separate read and write paths and clamping tran Memory cell with separate read and write paths and clamping tran

1987-01-14

1991-05-14

Gossage, Glenn

Static information storage and retrieval

Systems using particular element

Flip-flop

365155, 36518906, 36523005, 365226, G11C 11411

Patent

active

050162144

ABSTRACT:
Two pairs of bit lines are associated with each column of memory cells in a static random access memory (RAM) to provide separate paths for reading and writing operations or to provide a RAM having dual read ports. One pair of bit lines is connected to the emitters of the cross-coupled transistors in each cell to permit write operations to be carried out. The second pair of bit lines is connected to the collectors of clamping transistors which limit the collector voltage of the cell transistors, to permit data to be read.

REFERENCES:
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patent: 3675218 (1972-07-01), Sechler
patent: 4412312 (1983-10-01), Berger et al.
patent: 4480319 (1984-10-01), Hotta et al.
patent: 4635231 (1987-01-01), Mori et al.
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patent: 4754430 (1988-06-01), Hobbs
patent: 4779230 (1988-10-01), McLaughlin et al.
patent: 4833651 (1989-05-01), Seltzer et al.
Cavaliere et al., "Memory Cell Adapted for Different Combinations of Simultaneous Read and Write Operations", IBM Tech. Disc. Bull., vol. 23, No. 1, Jun. 1980, pp. 180-186.

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