Memory cell with reduced soft error rate

Details Memory cell with reduced soft error rate Memory cell with reduced soft error rate

2007-05-08

2007-05-08

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000, C257SE27098, C257SE21661

Reexamination Certificate

active

11063704

ABSTRACT:
The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.

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