Memory cell with reduced DIBL and Vss resistance

Details Memory cell with reduced DIBL and Vss resistance Memory cell with reduced DIBL and Vss resistance

2007-01-30

2007-01-30

Booth, Richard A. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S259000, C257SE21179

Reexamination Certificate

active

10915771

ABSTRACT:
According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.

REFERENCES:
patent: 5424233 (1995-06-01), Yang et al.
patent: 5502321 (1996-03-01), Matsushita
patent: 6635532 (2003-10-01), Song et al.
patent: 6759709 (2004-07-01), Shimizu
patent: 2003/0181028 (2003-09-01), Yeap et al.
patent: 0177 986 (1986-04-01), None
patent: 11067937 (1999-03-01), None
patent: WO 97/19472 (1997-05-01), None
U.S. Appl. No. 10/762,445, filed Jan. 22, 2004 Fang et al.

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