Memory cell with programmable antifuse technology

Details Memory cell with programmable antifuse technology Memory cell with programmable antifuse technology

1994-01-13

1995-06-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having fuse element

365 96, 365156, 257530, G11C 1716

Patent

active

054266149

ABSTRACT:
A memory cell (10) comprising a first antifuse (A1) operable to place the memory cell (10) in a non-volatile state. In one embodiment, the memory cell (10) comprises a pair of cross-coupled inverters (I1,I2). The first antifuse (A1)is connected between an output (B) of one of the cross-coupled inverters and ground and is operable to place the memory cell in a first non-volatile state. A second antifuse (A2) is connected between an output (B) and a supply voltage (Vcc) and is operable to place the memory cell (10) in a second non-volatile state. Only one of the antifuses, (A1 or A2) is programmed in memory cell (10).

REFERENCES:
patent: 4524377 (1985-06-01), Eguchi
patent: 4584669 (1986-04-01), Moynihan et al.
patent: 4841481 (1989-06-01), Ikeda et al.
patent: 5248632 (1993-09-01), Tung et al.
patent: 5299151 (1994-03-01), Ishihara et al.

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