Memory cell with power supply induced reversed-bias pass transis

Details Memory cell with power supply induced reversed-bias pass transis Memory cell with power supply induced reversed-bias pass transis

1995-07-05

1996-12-03

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365148, 365184, 365227, 365228, G11C 1100

Patent

active

055815006

ABSTRACT:
A memory cell is disclosed. The memory cell operating within a power supply range that induces the pass transistor(s) of the memory cell to be reversed biased when the memory cell is not being accessed. The memory cell includes a storage element capable of storing either a first data value or a second data value, a pass transistor, coupled to the storage element, and a power supply generator is coupled to the storage element. The power supply generator is configured to generate supply level voltages for the storage element so as to induce the pass transistor into a substantially reverse-biased state when the storage element is not being accessed, regardless of whether the storage element is storing the first data value or a second data value.

REFERENCES:
patent: 5020029 (1991-05-01), Ichinose et al.
FA 14.1: A Sub-0.5u A/MB Data-Retention DRAM, Hiroyuki Yamauchi et al., 1995 IEEE International Solid-State Circuits Conference, Session 14, Semiconductor Research Center, Matsushita Electric Industrial Co., Osaka, Japan, Feb. 17, 1995, pp. 244-245, 373.
FA14.2: A 29NS 64Mb DRAM with Hierarchical Array Architecture, Masayuki Nakamura et al., Hitachi Ltd., Tokyo, 1995 IEEE International Solid-State Circuits Conference, Session 14, Feb. 17, 1995, pp. 246-247, 373.
FA 14.3: Circuit Design Techniques for Low-Voltage Operating and/or Giga-Scale DRAMs, Tadato Yamagata et al., ULSI Laboratory, Mitsubishi Electric Corporation, Itami, Hyogo, Japan, 1995 IEEE International Solid-State Circuits Conference, Session 14, Feb. 17, 1995, pp. 248-249, 374.
Article entitled "Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's ", IEEE Journal of Solid State Circuits, vol. 29, No. 7, Jul. 1994, Takeshi Sakata et al., pp. 761-771.
Article entitled "Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAM's", IEEE Journal of Solid-State Circuits, vol. 29, No. 8, Aug. 1994, Takeshi Sakata et al., pp. 887-894.

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