Memory cell with increased capacitance

Details Memory cell with increased capacitance Memory cell with increased capacitance

2001-05-14

2003-01-21

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S230050

Reexamination Certificate

active

06510075

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory cells. More particularly, the invention relates to memory cells having improved retention time.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) such as digital signal processors (DSPs) include on-chip memory to store information. The on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC. Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes. A sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair.
FIG. 1
shows a conventional SRAM cell
101
. The SRAM cell comprises first and second transistors
110
and
120
coupled to a latch
130
, which stores a bit of information. One transistor is coupled to a bit line
140
and the other is coupled to a bit line complement
141
while the gates are coupled to a word line
135
. The latch includes first and second inverters
133
and
134
, each implemented with two transistors. As such, the SRAM cell is realized using six transistors.
Smaller SRAM cells using less than six transistors have been proposed to reduce chip size. However, the charge stored in such cells dissipates overtime. In order to restore the information stored in the cell, a refresh operation is required. Typically, refreshing of memory cells interrupts the normal operation, adversely impacting performance.
As evidenced from the above discussion, it is desirable to provide a memory cell with improved retention time.
SUMMARY OF THE INVENTION
The present invention relates to memory cells. More particularly, the invention relates to increasing the capacitance of memory cells to improve retention time. The memory cell, in accordance with one embodiment of the invention, comprises first and second access transistors coupled to respective first and second terminals of a storage transistor. The gate oxide of the storage transistor comprises a material having a high dielectric constant. The use of a high dielectric constant material as the gate oxide increases the capacitance of the storage capacitor.


REFERENCES:
patent: 5717638 (1998-02-01), Kim
patent: 5757694 (1998-05-01), Mitani
patent: 5761113 (1998-06-01), Natsume et al.
patent: 5812476 (1998-09-01), Segawa

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