Static information storage and retrieval – Systems using particular element – Flip-flop
Patent
1990-04-06
1991-08-13
Popek, Joseph A.
Static information storage and retrieval
Systems using particular element
Flip-flop
365156, 365190, G11C 1140
Patent
active
050401459
ABSTRACT:
A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read sense lines further includes a timed, active write load. The memory cell includes first and second NPN bipolar transistors having commonly connected emitters, and cross-coupled bases and collectors; and first and second PNP bipolar transistors configured as loads for the pair of NPN bipolar transistors. Write transistors are provided responsive to the write enable signal for draining current from a selected one of the first or second nodes. Transistors connected as diodes between the PNP bases and each of the cross-coupled NPN nodes are responsive to the current draining effected by the write transistors for biasing both of the first and second PNP transistors into an active mode of operation.
REFERENCES:
patent: 3643235 (1971-02-01), Berger et al.
patent: 3725879 (1973-04-01), Martin
patent: 3801967 (1974-04-01), Berger et al.
patent: 3815106 (1974-06-01), Wiedmann
patent: 4158237 (1979-06-01), Wiedmann
patent: 4228525 (1980-10-01), Kawarada et al.
patent: 4387445 (1983-06-01), Denis et al.
patent: 4419745 (1983-12-01), Toyoda et al.
patent: 4575821 (1986-03-01), Eden et al.
patent: 4607350 (1986-08-01), Scianna
patent: 4754430 (1988-06-01), Hobbs
patent: 4782467 (1988-11-01), Bett et al.
patent: 4783765 (1988-11-01), Werner
patent: 4813017 (1989-03-01), Wong
patent: 4858181 (1989-08-01), Scharrer et al.
patent: 4922455 (1990-05-01), Chin et al.
J. A. Porter et al., "AC Write Scheme for BiPolar Random Access Memories Using Schottky Coupled Cells", IBM Technical Disclosure Bulletin, vol. 23, No. 11, Apr. 1981, pp. 4960-4962.
B. W. Martin et al., "Low Leakage Complementary Transistor Switch Cell", IBM Technical Disclosure Bulletin, vol. 26, No. 7A, Dec. 1983, pp. 3229-3230.
IBM Technical Disclosure Bulletin, vol. 10, No. 4, Sept. 1977 by J. R. Cavaliere et al., pp. 1447-1450.
IBM Technical Disclosure Bulletin, vol. 16, No. 12, May 1974 by H. H. Berger et al., pp. 3965-3967.
IBM Technical Disclosure Bulletin, vol. 16, No. 12, May 1974, by Berger et al., pp. 3963-3964.
IBM Technical Disclosure Bulletin, vol. 19, No. 1, June 1976 by J. E. Gersbach, p. 34.
IBM Technical Disclosure Bulletin, vol. 14, No. 6, Nov. 1972, by S. K. Wiedmann, pp. 1707-1708.
IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972 by H. H. Berger et al., pp. 3542-3543.
IBM Technical Disclosure Bulletin, vol. 14, No. 6, Nov. 1971, by J. J. McDowell, p. 1678.
Andersen John E.
Barry Robert L.
Bisnett James N.
Fung Eric G.
Brandt Jeffrey L.
International Business Machines - Corporation
Popek Joseph A.
LandOfFree
Memory cell with active write load does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory cell with active write load, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell with active write load will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1532316