Memory cell with active device for saturation capacitance discha

Static information storage and retrieval – Systems using particular element – Flip-flop

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365175, 36518906, 365204, G11C 1100

Patent

active

049224557

ABSTRACT:
A transistor memory cell is disclosed of the type wherein an unclamped conducting transistor in each of a plurality of memory cells connected to a given word line is driven into saturation when storing data. The cell is equipped with controlled active devices for discharging the saturation capacitance of the conducting transistors prior to writing new data into the cells. Each active device is characterized with a forward low-impedance current direction and reverse high impedance current direction therethrough for each saturation transistor. Each active device is connected to discharge an associated saturation transistor in its forward current direction. In one embodiment, each active device discharges to a word line when the line is brought to an appropriate control potential. In another embodiment, each active device discharges to a separate discharge line not connected to the work line when the former line is brought to an appropriate control potential. The active devices may be diodes. In yet a further embodiment, the active devices may comprise diodes with leaky reverse bias characteristics. These diodes, in their reverse bias current direction, may be used as the memory cell loads. Alternatively, a PNP transistor may be used as the memory cell load. Resistors may be included in the discharge line to prevent word line-bit line voltage clamping.

REFERENCES:
patent: 3510849 (1970-05-01), Igarashi
patent: 3585412 (1971-06-01), Hodges et al.
patent: 3671772 (1972-06-01), Henle
patent: 3703709 (1972-11-01), Matsue
patent: 3849675 (1974-11-01), Waaben
patent: 3969707 (1976-07-01), Lane et al.
patent: 3973246 (1976-08-01), Millhollan et al.
patent: 4023148 (1977-05-01), Hueber et al.
patent: 4057789 (1977-11-01), Spadavecchia et al.
patent: 4090255 (1978-05-01), Berger et al.
patent: 4127899 (1978-11-01), Dachtera
patent: 4308595 (1981-12-01), Houghton
patent: 4393471 (1983-07-01), Hart et al.
patent: 4400712 (1983-08-01), O'Connor
patent: 4439842 (1984-03-01), Malaviya
patent: 4479200 (1984-10-01), Sato et al.
patent: 4480319 (1984-10-01), Hotta et al.
patent: 4538244 (1985-08-01), Sugo et al.
patent: 4575821 (1986-03-01), Eden et al.
patent: 4592023 (1986-05-01), Beranger et al.
patent: 4598390 (1986-07-01), Chan
patent: 4635228 (1987-01-01), Jordy
IBM Technical Disclosure Bulletin, vol. 22, No. 1, Jun. 1979, Denis et al., Random-Access Memory Cell for Medium Performance Applications.
IBM Technical Disclosure Bulletin, vol. 13, No. 2, Jul. 1970, Shepard et al., FET Memory Cell Using Schottky Diodes as Load Devices.
IBM TDB, vol. 28, No. 8, Jan. 1986, pp. 3350-3351, Kneeper et al.
Kolchak, IBM TDB, vol. 17, No. 4, 9/74, pp. 1058-1059.
Eardley-IBM TDB, vol. 21, No. 11, Apr. 1979, pp. 4529-4530.

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