Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-30
2003-06-24
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S304000, C257S307000, C257S301000, C257S347000, C257S353000, C438S238000, C438S243000, C438S244000, C438S388000, C438S391000
Reexamination Certificate
active
06583464
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
In memory cell arrays, in particular in DRAM arrays, information is stored in the form of electrical charges in the individual memory cells. In many of such cells, the electrical charge is stored in memory capacitors. Here, the charge is retained in the memory capacitor for only a limited time. In DRAM arrays the retention time in a memory capacitor is approximately 2 to 3 seconds. In order to retain the stored information for longer, the information is periodically refreshed.
It has become apparent that individual memory cells in memory cell arrays have fluctuating retention times. Therefore, the retention time in the memory cells fluctuates between very small values, for example 10 milliseconds, and customary retention times of 2 to 3 seconds. This fault, which is also referred to as a variable retention time failure, is not predictable.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell array and method for fabricating it which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which fluctuations in the retention time of a stored charge are reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell array having memory cells, including: a capacitor electrode formed of a polycrystalline semiconductor material; a monocrystalline semiconductor region forming an electrical connection with the polycrystalline semiconductor material of the capacitor electrode; and islands formed of an amorphous material disposed in an area of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region.
In a memory cell array having memory cells in which there is an electrical connection between the polycrystalline semiconductor material of the capacitor electrode and the monocrystalline semiconductor region, islands made of amorphous material are disposed in the vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands made of amorphous material stabilize the boundary face between the monocrystalline semiconductor region and the polycrystalline semiconductor material of the capacitor electrode. This avoids the situation during the fabrication process, in particular during heat-treatment steps, in which the boundary face between the polycrystalline semiconductor material and the monocrystalline semiconductor region changes in such a way that on the one hand epitaxial growth emanating from the surface of the monocrystalline semiconductor region extends into the polycrystalline semiconductor material, and on the other hand granular growth emanating from the polycrystalline semiconductor material extends into the monocrystalline semiconductor region.
Preferably, the islands are disposed in the vicinity of the electrical connection in a planar configuration in an irregular grid.
The islands may have various shapes. In particular, the islands may be conical, ellipsoidal, rotationally ellipsoidal or of irregular shape. In particular, the various islands may have different shapes.
The invention is based on the following ideas: the variable retention time failure effect is observed in the memory cells in which there is an electrical connection between a monocrystalline semiconductor region and polycrystalline semiconductor material of a capacitor electrode. It is observed in particular in memory cells in which a selection transistor is disposed in a monocrystalline semiconductor substrate, the one source/drain region of the selection transistor is electrically connected to a capacitor electrode which is disposed in a trench and is made of polycrystalline semiconductor material. The variable retention time failure effect also occurs in memory cells with a stacked capacitor.
Investigations have shown that memory cells with a variable retention time failure effect in the monocrystalline semiconductor region exhibit crystal defects which emanate from the boundary face between the monocrystalline semiconductor region and the polycrystalline semiconductor material. The defects are considered to be a consequence of the unstable boundary faces between the polycrystalline semiconductor material and the monocrystalline semiconductor region.
According to the invention, islands made of amorphous material are disposed between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands cause mechanical tension both on the surface of the monocrystalline semiconductor region and on the surface of the polycrystalline semiconductor material. In heat-treatment processes, the mechanical tension on the aforesaid surfaces prevents epitaxial growth emanating from the surface of the monocrystalline semiconductor region and granular growth emanating from the polycrystalline semiconductor material. As a result of the granular growth emanating from the polycrystalline semiconductor material, the crystal lattice defect that is present in the polycrystalline semiconductor material is transferred into the monocrystalline semiconductor region. The epitaxial growth emanating from the surface of the monocrystalline semiconductor region into the polycrystalline semiconductor material also brings about defects in the crystal in the monocrystalline semiconductor region. These defects, which may lead inter alia to dislocations, are avoided in the memory cell array according to the invention by the provision of the islands made of amorphous material.
At the same time, the islands made of amorphous material ensure that there is an electrical contact between the polycrystalline semiconductor material and the monocrystalline semiconductor region, since charge carriers can migrate through, between the islands made of amorphous material, from the polycrystalline semiconductor material into the monocrystalline semiconductor region. Furthermore, diffusion of doping material between the polycrystalline semiconductor material and the monocrystalline semiconductor region is possible.
Both insulating material, in particular SiO
2
or Si
3
N
4
, and conductive material, in particular tungsten or another metal with a high melting point, are suitable for the islands made of amorphous material.
The monocrystalline semiconductor region is in particular part of a semiconductor substrate, which has monocrystalline silicon at least in the vicinity of the electrical connection. A monocrystalline silicon wafer or a monocrystalline silicon layer of an SOI substrate are, inter alia, suitable as a semiconductor substrate.
The islands made of the amorphous material are preferably formed from oxide, in particular from silicon dioxide.
During the fabrication of the memory cell array, an amorphous layer of a predefined thickness is preferably applied to the surface of the monocrystalline semiconductor region in the vicinity of the electrical connection. Polycrystalline semiconductor material is applied on top of this. Here, the amorphous layer ensures that the polycrystalline semiconductor material grows in a polycrystalline fashion. In order to form the islands made of the amorphous material, preferably a heat-treatment step is carried out, during which step the amorphous layer breaks up into the islands.
Such a formation of oxide islands from a previously continuous oxide layer by a heat-treatment process is already known, in conjunction with bipolar transistors, from H. Schaber et al., IEDM 1987, pages 170 to 173. Such a heat-treatment step is used to break up the so-called native oxide layer or layer which arises when the substance is exposed to air and is formed uncontrollably on exposed silicon surfaces. The native oxide layer leads to increased resistance values between the emitter and the emitter connection on the surface of the emitter in bipolar transistors. The thermal breaking up of the layer of oxide that arises when the substance is exposed to air in the case o
Beckmann Gustav
Bertagnolli Emmerich
Bianco Michael
Klose Helmut
Greenberg Laurence A.
Infineon - Technologies AG
Lee Eddie
Mayback Gregory L.
Ortiz Edgardo
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