Memory cell transistor having different source/drain...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S306000

Reexamination Certificate

active

06949783

ABSTRACT:
A memory cell transistor of a DRAM device is provided. A gate stack pattern is formed on a semiconductor substrate. A DC node and a BC node are formed substantially under lateral sides of the gate stack pattern in the semiconductor substrate. The DC node and the BC node are being electrically connected to a bit line and a storage electrode of a capacitor respectively. A first source/drain junction region is formed under the DC node and a second source/drain junction region is formed under the BC node. The first source/drain junction region has a profile which is different from that of the second source/drain junction region.

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patent: 6380045 (2002-04-01), Guo
patent: 02-281654 (1990-11-01), None

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