Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-04-22
2008-04-22
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S719000, C714S710000, C714S721000, C714S723000
Reexamination Certificate
active
07363555
ABSTRACT:
A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input/output lines based on a test mode signal and a plurality of control clock signals; a logic operation unit for performing a logic operation to the data outputted to the plurality of global input/output lines and for outputting a result of the logic operation to a test global input/output line; and a switching unit coupled to the test global input/output line and the plurality of global input/output lines for selectively passing data of the test global input/output line and data of the global input/output lines based on the test mode signal and the plurality of control clock signals.
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Blakely , Sokoloff, Taylor & Zafman LLP
Britt Cynthia
Hynix / Semiconductor Inc.
Merant Guerrier
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