Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-20
2003-12-09
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S906000
Reexamination Certificate
active
06661050
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for fabricating memory cell structures within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for fabricating, with enhanced performance, memory cell structures within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates over which are formed patterned conductor layers which are separated by dielectric layers.
Ubiquitous in the art of semiconductor integrated circuit microelectronic fabrication are memory cell structures which are employed when fabricating memory cells within semiconductor integrated circuit microelectronic fabrications. Memory cell structures within semiconductor integrated circuit microelectronic fabrications typically comprise a field effect transistor (FET) device as a switching element. Within a memory cell structure, one of the source/drain regions within the field effect transistor (FET) device is electrically connected to a storage capacitor, while the other of the source/drain regions within the field effect transistor (FET) device is electrically connected to a bitline within the memory cell structure. Finally, a gate electrode within the field effect transistor (FET) device serves as a wordline within the memory cell structure.
While memory cell structures are thus clearly desirable in the art of semiconductor integrated circuit microelectronic fabrication and often essential in the art of semiconductor integrated circuit microelectronic fabrication, memory cell structures are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication. In that regard, memory cell structures are often difficult to fabricate within semiconductor integrated circuit microelectronic fabrications with enhanced performance, in particular within the context of decreased semiconductor substrate areal dimensions.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to fabricate within semiconductor integrated circuit microelectronic fabrications memory cell structures with enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various memory cell structures, and methods for fabrication thereof, have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication.
Included among the memory cell structures and methods for fabrication thereof, but not limited among the memory cell structures and methods for fabrication thereof, are memory cell structures and methods for fabrication thereof disclosed within Dennard et al., in U.S. Pat. No. 5,198,995 (a dynamic random access memory (DRAM) cell structure which employs a trench capacitor structure which in part comprises a semiconductor substrate); and Leung et al., in “The Ideal SoC Memory: 1T-SRAM,” IEEE 0-7803-6598-4/00 (2000) (a static random access memory (SRAM) cell structure which employs a planar capacitor structure which in part comprises a semiconductor substrate).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional memory cell structures, and methods for fabrication thereof, which may be fabricated with enhanced performance.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a memory cell structure, and a method for fabricating the memory cell structure, for use within a semiconductor integrated circuit microelectronic fabrication.
A second object of the present invention is to provide a memory cell structure and a method for fabrication thereof in accord with the first object of the present invention, wherein the memory cell structure is fabricated with enhanced performance.
A third object of the present invention is to provide a memory cell structure and a method for fabrication thereof in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a memory cell structure and a method for fabricating the memory cell structure.
To practice the method of the present invention, there is first provided a semiconductor substrate having formed therein a trench which adjoins an active region of the semiconductor substrate. There is then ion implanted the semiconductor substrate to form therein a doped well which includes the active region of the semiconductor substrate and the trench. There is then formed into the trench a capacitive dielectric layer having formed thereupon a capacitor plate layer. Finally, there is also formed within and upon the active region of the semiconductor substrate a field effect transistor (FET) device, where a source/drain region within the field effect transistor (FET) device is electrically connected with the capacitor plate layer.
The method of the present invention contemplates a memory cell structure fabricated in accord with the method of the present invention.
The present invention provides a memory cell structure, and a method for fabrication thereof, for use within a semiconductor integrated circuit microelectronic fabrication, wherein the memory cell structure is formed with enhanced performance.
The present invention realizes the foregoing objects by forming within a memory cell structure for use within a semiconductor integrated circuit microelectronic fabrication a storage capacitor within a trench adjoining an active region of a semiconductor substrate, wherein both the active region and the trench are included within a doped well formed within the semiconductor substrate.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally known in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific process sequencing to provide a specific memory cell structure in accord with the present invention. Since it is thus at least in part a specific process sequencing and a specific memory cell structure which provide at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 4922460 (1990-05-01), Furutani et al.
patent: 5182224 (1993-01-01), Kim et al.
patent: 5198995 (1993-03-01), Dennard et al.
patent: 6097076 (2000-08-01), Gonzaler et al.
patent: 6200851 (2001-03-01), Arnold
patent: 6475865 (2002-11-01), Yang et al.
MoSys Inc. “The Ideal SoC Memory: 1T-SRAM”, 2000 IEEE, pp. 32-36.
Chang Chung-Wei
Tzeng Kuo-Chyuan
Wang Chen-Jong
Nhu David
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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