Memory cell structure of metal programmable read only memory...

Details Memory cell structure of metal programmable read only memory... Memory cell structure of metal programmable read only memory...

2002-02-28

2004-08-03

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read only systems

C365S063000, C365S072000, C365S103000, C257S530000

Reexamination Certificate

active

06771528

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-30523, filed May 31, 2001, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory devices and more particularly, to memory cell structures of metal programmable read only memories (ROMs).
BACKGROUND OF THE INVENTION
A Mask Read Only Memory (Mask ROM) is a semiconductor memory device in which data required is coded during a manufacturing process. There are, generally, two types of Mask ROMs: an embedded diffusion-programmable ROM and an embedded metal programmable ROM. Whether a mask ROM is an embedded diffusion-programmable ROM or an embedded metal programmable ROM, depends on the manufacturing process. Specifically, in the case of the embedded diffusion programmable ROM, its ROM data is programmed during a diffusion process, whereas in the case of the embedded metal programmable ROM, its ROM data is programmed during a metal/metallization process. Additionally, in an embedded via programmable ROM, which is similar to the embedded metal programmable ROM, its ROM data code is programmed during a via process.
Generally, the embedded diffusion-programmable ROM has been preferred to the embedded metal programmable ROM, mainly because the integration density of the former is typically higher than that of the latter by about from 25% to 35%.
However, compared to the embedded metal programmable ROM, it typically takes more time to manufacture the embedded diffusion-programmable ROM after data is received from a user. Recently, increased interest has been shown in the embedded metal (or via) programmable ROM, not only because the integration density thereof has been largely improved as techniques of manufacturing semiconductors have developed, but also because it is advantageous in terms of “Time-to-Market.”
FIG. 1
illustrates a two-column bit memory cell structure of a conventional embedded metal programmable ROM. Referring to
FIG. 1
, a conventional metal programmable ROM includes first and second word lines WL
1
and WL
2
, first and second bit lines BL
1
and BL
2
, a virtual grounding line VGND and first through fourth NMOS cell transistors n
11
-n
14
.
A first side of each of the first through fourth NMOS cell transistors n
11
-n
14
is connected to the virtual grounding line VGND. Also, the gates of the first and third cell transistors n
11
and n
13
and the gates of the second and fourth cell transistors n
12
and n
14
are connected to the first word line WL
1
and the second word line WL
2
, respectively.
Referring to
FIG. 1
, data 0, 1 and data 0, 0 are coded in two bit cells selected by the first word line WL
1
and two bit cells selected by the second word line WL
2
, respectively. When the data 0, 1 is coded in two bit cells selected by the first word line WL
1
, the second side of the first cell transistor n
11
is connected to the first bit line BL
1
and the second side of the first cell transistor n
13
is floated. On the other hand, when the data 0, 0 is coded in two bit cells selected by the second word line WL
2
, the second sides of the second cell transistor n
12
and the fourth cell transistor n
14
are connected to the first bit line BL
1
and the second bit line BL
2
, respectively.
FIG. 2
shows a four-column bit memory structure of a conventional metal programmable ROM. Referring to
FIG. 2
, the four-column bit memory cell of a conventional metal programmable ROM includes first and second word lines WL
1
and WL
2
, first and second bit lines BL
1
and BL
2
, first to third virtual grounding lines VGND
1
-VGND
3
and first through eighth NMOS cell transistors n
21
-n
28
.
A first side of each of the first and second cell transistors n
21
-n
22
is connected to the first virtual grounding line VGND
1
. A first side of each of the third through sixth NMOS cell transistors n
23
-n
26
and a first side of each of the seventh and eighth cell transistors n
27
and n
28
are connected to the second virtual grounding line VGND
2
and the third virtual grounding line VGND
3
, respectively.
Further, the first word line WL
1
is connected to the gates of the first, third, fifth and seventh cell transistors n
21
, n
23
, n
25
and n
27
and the second word line WL
2
is connected to the gates of the second, fourth, sixth and eight cell transistors n
22
, n
24
, n
26
and n
28
.
FIG. 2
shows that data 0, 0, 1, 0 and 1, 0, 1, 1 are coded in four bit cells selected by the first word line WL
1
and four bit cells selected by the second word line WL
2
. If data 0, 0, 1, 0 are coded in four bit cells selected by the first word line WL
1
, the second sides of the first and third cell transistors n
21
and n
23
are connected to the first bit line BL
1
, the second side of the fifth cell transistor n
25
is floated and the second side of the seventh cell transistor n
27
is connected to the second bit line BL
2
. On the other hand, when data 1, 0, 1, 1 are coded in four bit cells selected by the second word line WL
2
, the second sides of the second, sixth and eighth cell transistors n
22
, n
26
and n
28
are floated and the second side of the fourth cell transistor n
24
is connected to the first bit line BL
1
.
The above-described conventional metal programmable ROMs, however, may have a disadvantage in that the size thereof may be larger than that of a conventional embedded diffusion programmable ROM because diffusion domains that hold a bit line in common are separated from one another. Furthermore, the reading speed may be increased over that of a conventional embedded diffusion programmable ROM due to an increase in the loaded capacitance of a bit line which may also result in an increase in power consumption.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a memory cell structure of a metal programmable ROM that includes a word line, a bit line, first and second virtual grounding lines and a cell transistor. The cell transistor has a first side connected to the bit line. The cell transistor provides a first bit cell selected by signals of the word line and the first virtual grounding line and a second bit cell selected by signals of the word line and the second virtual grounding line.
In further embodiments of the present invention, a grounding line is also provided. In such embodiments, a second side of the cell transistor is selectively floated or connected to one of the first virtual grounding line, the second virtual grounding line and/or the grounding line, and the gate of the cell transistor is connected to the word line.
In further embodiments of the present invention, a memory cell structure of a metal programmable ROM is provided having first and second word lines, a bit line, a grounding line and first and second virtual grounding lines. A first cell transistor having a drain connected to the bit line and a gate connected to the first word line and a second cell transistor having a drain connected to the bit line and a gate connected to the second word line are also provided.
In such embodiments, a source of the first cell transistor may be floated or connected to one of the first virtual grounding line, the second virtual grounding line and/or the grounding line. Furthermore, a source of the second cell transistor may be floated or connected to one of the first virtual grounding line, the second virtual grounding line and/or the grounding line.
The first cell transistor may be shared by both a first bit cell selected by the first word line and the first virtual grounding line and a second bit cell selected by the first word line and the second virtual grounding line. Similarly, the second cell transistor may be shared both by a third bit cell selected by the second word line and the first virtual grounding line and a fourth bit cell selected by the second word line and the second virtual grounding line.
In additional embodiments of the present invention, a memory cell structure of a metal programmable ROM is provided having first and second word l

Affiliated with

Also associated with

Rating

Memory cell structure of metal programmable read only memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cell structure of metal programmable read only memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell structure of metal programmable read only memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3356982