Memory cell structure of a mask programmable read only...

Details Memory cell structure of a mask programmable read only... Memory cell structure of a mask programmable read only...

1999-06-16

2001-03-20

Hardy, David (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S276000

Reexamination Certificate

active

06204540

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a memory cell structure of a mask programmable read only memory and a mask ROM coding method.
A non-volatile semiconductor memory device has memory cells, each of which has a field effect transistor such as a MOS field effect transistor serving as a switching device and a capacitor for storing any one of two different voltage levels representing 1-bit binary digit information. The two different voltage levels depend upon an ON or OFF state of the MOS field effect transistor.
In order to set a threshold voltage level for ON and OFF switching operations of the MOS field effect transistor, a selective ion-implantation to a channel region of the MOS field effect transistor is carried out by use of a mask. Such ion-implantation into the channel region of the MOS field effect transistor for the purpose of setting or controlling the threshold voltage level for ON and OFF switching operations of the MOS field effect transistor is so called to be code ion-implantation.
The mask to be used for the ROM coding through the code ion-implantation is carried out as follows. After a gate electrode of the MOS field effect transistor has been formed or an inter-layer insulator has been formed over the gate electrode, then a resist such as a photo-resist is applied and then an opening is formed in the photo-resist so that the opening is positioned over the channel region of the MOS field effect transistor to form a photo-resist pattern. Assuming that the MOS field effect transistor is of the n-channel type, ions including boron are implanted by use of the photo-resist pattern as a mask. This ROM coding method has been known and is, for example, disclosed in Japanese laid-open patent publication No. 6-268178.
FIG. 1A
is a fragmentary plane view illustrative of a conventional flat-structure memory cell of a mask programmable read only memory device.
FIG. 1B
is a fragmentary cross sectional elevation view illustrative of the conventional flat-structure memory cell taken along an M-N line of FIG.
1
A.
The above memory cell structure is formed over a p-type semiconductor substrate
101
. A plurality of stripe-shaped n+-type diffusion regions
102
selectively extend in an upper region of the p-type semiconductor substrate
101
so that the stripe-shaped n+-type diffusion regions
102
are aligned at a constant pitch and in parallel to each other, wherein each of the stripe-shaped n+-type diffusion regions
102
has a longitudinal direction along a first direction. A plurality of gate electrodes
104
selectively extend over the gate oxide film
103
so that the gate electrodes
104
are aligned at a constant pitch and in parallel to each other, wherein each of the gate electrodes
104
has a longitudinal direction along a second direction perpendicular to the first direction. A plurality of stripe-shaped p-type diffusion regions
105
selectively extend in the upper region of the p-type semiconductor substrate
101
except under the gate electrodes
104
. The stripe-shaped p-type diffusion regions
105
are provided for isolating adjacent two of the stripe-shaped n+-type diffusion regions
102
from each other so that the stripe-shaped p-type diffusion regions
105
are aligned at a constant pitch and in parallel to each other, wherein each of the stripe-shaped p-type diffusion regions
105
has a longitudinal direction along the second direction.
An inter-layer insulator
106
extends entirely over the gate electrodes
104
and the semiconductor substrate
101
. A resist mask
107
is provided over the inter-layer insulator
106
, wherein the resist mask
107
has a square-shaped opening
108
which is positioned over a channel region under the gate electrode
104
. The resist mask
107
with the square-shaped opening
108
is used as a mask for carrying out the ROM code ion-implantation to form a ROM code diffusion region
109
. This ROM code diffusion region
109
extends in a selected upper region of the semiconductor substrate
101
and under the gate electrode
104
and parts of the p-type diffusion regions
105
.
FIGS. 2A through 2D
are fragmentary cross sectional elevation views illustrative of the conventional flat-structure memory cells in sequential steps involved in a conventional method of forming the conventional flat-structure memory cell of
FIGS. 1A and 1B
.
With reference to
FIG. 2A
, the stripe-shaped n+-type diffusion regions
102
not illustrated are selectively formed in an upper region of the p-type semiconductor substrate
101
so that the stripe-shaped n+-type diffusion regions
102
are aligned at a constant pitch and in parallel to each other, wherein each of the stripe-shaped n+-type diffusion regions
102
has a longitudinal direction along a first direction. A gate oxide film
103
is formed by a thermal oxidation. A plurality of the gate electrodes
104
are selectively formed over the gate oxide film
103
by photolithography technique and subsequent dry etching process, so that the gate electrodes
104
are aligned at a constant pitch and in parallel to each other, wherein each of the gate electrodes
104
has a longitudinal direction along a second direction perpendicular to the first direction. The gate electrodes
104
may comprise polysilicon films or refractory metal polycide film.
With reference to
FIG. 2B
, the gate electrodes
104
are used as masks for ion-implantation of boron and subsequent heat treatment whereby the stripe-shaped p-type diffusion regions
105
are selectively formed in the upper region of the p-type semiconductor substrate
101
except under the gate electrodes
104
for isolating adjacent two of the stripe-shaped n+-type diffusion regions
102
from each other so that the stripe-shaped p-type diffusion regions
1
.
05
are aligned at a constant pitch and in parallel to each other, wherein each of the stripe-shaped p-type diffusion regions
105
has a longitudinal direction along the second direction.
With reference to
FIG. 2C
, a silicon oxide film is entirely deposited by a chemical vapor deposition method to form the inter-layer insulator
106
which extends entirely over the gate electrodes
104
and the semiconductor substrate
101
.
With reference to
FIG. 2D
, a resist mask
107
is provided over the inter-layer insulator
106
, wherein the resist mask
107
has a square-shaped opening
108
which is positioned over a channel region under the gate electrode
104
. The resist mask
107
with the square-shaped opening
108
is used as a mask for carrying out the ROM code ion-implantation into a selected region under the gate electrode
104
and parts of the p-type diffusion regions
105
. A heat treatment is carried out for thermal diffusion to form a ROM code diffusion region
109
. This ROM code diffusion region
109
extends in a selected upper region of the semiconductor substrate
101
and under the gate electrode
104
and parts of the p-type diffusion regions
105
. The provision of the ROM code diffusion region
109
increases a threshold voltage of the MOS field effect transistor.
As well illustrated in
FIG. 2D
, the ROM code diffusion region
109
extends not only under the gate electrode
104
but also under parts of the p-type diffusion regions
105
, even the ROM code diffusion region
109
is intended to be formed but only under the gate electrode
104
. For the above described conventional technique, it is difficult to limit the ROM code diffusion region
109
into the channel region under the gate electrode
104
. The expansion in the lateral direction of the ROM code diffusion region
109
, however, causes a variation in threshold voltage from the intended or designed value.
FIG. 3A
is a fragmentary plane view illustrative of the above conventional mask ROM coding ion-implantation to form the conventional flat-structure memory cell of the mask programmable read only memory device of FIG.
1
A.
FIG. 3B
is a fragmentary cross se

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