Memory cell structure for semiconductor memory device

Details Memory cell structure for semiconductor memory device Memory cell structure for semiconductor memory device

1998-12-22

2001-06-12

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S755000

Reexamination Certificate

active

06246087

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory cell structure of semiconductor memory device, and particularly to a memory cell structure of semiconductor memory device and fabricating method thereof suitable to a highly integrated memory device by using a line patterning method to overcome a resolution limitation.
2. Description of the Conventional Art
There have been proposed many kinds of cell arrays and structures for a highly integrated semiconductor dynamic random access memory (DRAM) device.
The conventional semiconductor memory device as shown in
FIG. 1A and 1B
adopts a capacitor under bit line (CUB) structure in which a capacitor is formed in a rectangular active region a on a silicon substrate, and then a bit line is formed. In the figure, the capacitor consists of a node electrode
1
a
and a plate electrode
1
b
. The reference signal WL designates word lines. In a memory cell of the CUB structure, the capacitor being below the bit lines, is restricted in its area. In order to obtain the same capacitance in a highly integrated memory device as in an existing one, it is required to increase the topology of the capacitor. However, this results in an increase of the aspect ratio of the bit line contact hole, which is accompanied by a technical difficulty in filling up the contact hole with a conductive layer and in line patterning. therefore, such a memory cell structure is not suitable for a highly integrated memory device.
For 16M or 64M DRAM semiconductor elements, a new cell array and a structure thereof are required.
FIGS. 2A and 2B
show a semiconductor memory element of a capacitor over bit line (COB) structure as disclosed in U.S. Pat. No. 5,140,389 which designed to increase the capacitance by first forming the bit lines and securing the area for the capacitor above the upper part of the bit lines (BL). The capacitor consists of a node electrode
1
a
and a plate electrode
1
b
. In such structure, it is inevitably to design the active region a in a diagonal form so as to make the bit lines (BL) and word lines (WL) cross after the capacitor is formed on the bit line BL. Consequently, there have arisen the problems that the phenomena of a significant reduction or distortion of the pattern can occur upon forming the active region a in a diagonal form, it is difficult to secure space for the active regions and to form an exact pattern, and the packing density is reduced. For this reason, a new memory cell array and structure is required for a very highly integrated memory device (256M or more DRAM).
As shown in
FIGS. 3A
to
3
I, the memory cells for semiconductor memory devices adopting the COB structure as shown in
FIG. 2
are fabricating through the following steps:
(a) implanting boron ions B
+
into the substrate
1
. forming an oxide film
2
of SiO2 on the substrate
1
in a thickness of about 100 Å, and then depositing a nitride film
3
of Si3N4 in a thickness of about 1400 Å by means of a low-pressure chemical vapor deposition (LPCVD);
(c) patterning the active regions a by forming a photoresist layer
4
on the nitride film
3
, and then forming a field channel stop layer by implanting boron into the substrate;
(d) removing the patterned photoresist layer
4
, removing the nitride film
3
after forming a field oxide film
5
, and then growing a gate oxide film
6
in a thickness of about 100 Å;
(e) depositing a doped polysilicon on the substrate
1
, forming gate electrodes
7
on the active regions by patterning the polysilicon, and then forming lightly doped source/drain regions which are lightly doped drain (LDD) regions, by means of ion-implantation of phosphorous ions P+;
(f) depositing an insulation film on the surface of the substrate
1
, forming side wall spacers on the gate electrode
7
, and then forming doped n+ source/drain regions by implanting arsenic ions As+ into the substrate
1
;
(g) coating an insulation film
10
on the surface of the semiconductor substrate
1
, forming contact holes for bit line contact by exposing a part of each active region of the substrate
1
, forming sequentially a polysilicon film
11
, a tungsten silicide WSi2 film and an insulation film
13
so as to fill up the contact hole, and forming, after patterning the insulation film
13
, the bit lines in the polysilicon film
11
and then the tungsten silicide film
12
using the insulation film
13
as mask;
(h) forming contact holes by exposing a part of the substrate
1
on which the bit lines are formed, depositing and patterning a polysilicon film
14
on the substrate
1
so as to fill up the contact holes and to form the capacitor node electrodes; and
(i) depositing a dielectric film
15
on the node electrodes, forming a plate electrode of the capacitors, and depositing a polysilicon film
16
on the dielectric film
15
.
The semiconductor memory device adopting the conventional COB structure as described above, has problems in that because the active pattern is in a diagonal form and has so many corners, a considerable reduction or distortion of pattern can occur, the photolithography process is difficult, and the packing density to be formed in the same area is so los that it is disadvantageous to a high integration device.
SUMMARY OF THE INVENTION
The object of the present invention is to eliminate the problems in the memory cell structure for semiconductor memory device and fabricating method thereof in the conventional COB structure, and to provide a memory cell structure for semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration.
To achieve the above object, there is provided a memory cell structure for a semiconductor memory device which includes a semiconductor substrate having a first conductivity type, including a plurality of active regions each having a first diffusion region and a second diffusion region which form a transistor, and an isolation region; a plurality of word lines formed on the semiconductor substrate and each acting as a gate electrode of a corresponding transistor; a first insulation film formed on the semiconductor substrate and the word lines; a contact hole formed to expose the first diffusion region through the first insulation film; a plurality of bit lines crossingly arranged above the word lines and contacting with a corresponding first diffusion region via a corresponding contact hole wherein each bit line includes a first bit line of a pad type contacting with the first diffusion region and a second bit line contacting with the first bit line over the isolation region in a straight line form; a second insulation film formed on the plurality of bit lines and the first insulation film; an electrode contact hole formed to expose the second diffusion region through the first and the second insulation film; a capacitor lower electrode formed on the second insulation film and contacting with a corresponding second diffusion region via a corresponding electrode contact hole; a capacitor dielectric layer formed on the capacitor lower electrode; and a capacitor upper electrode formed on the capacitor dielectric layer.
A preferred embodiment of semiconductor device fabricating method according to the present invention to attain the above object comprises the following steps of forming a gate electrode and first and second diffusion regions of a transistor on a semiconductor substrate, depositing a first insulation film on the semiconductor substrate, forming a first contact hole in the first insulation film by exposing the first diffusion region, depositing a first conductive layer on a surface of the first insulation film, filling up the first contact hole, forming on the first conductive layer a mask layer for forming a first bit line pattern, the mask having an etch selectivity different from the conductive layer, forming a photoresist layer for formation of a second bit line, in such way that a part of the photore

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