Memory cell structure and semiconductor memory device

Details Memory cell structure and semiconductor memory device Memory cell structure and semiconductor memory device

2008-07-29

2008-07-29

Sefer, A. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S311000, C257SE21008, C257SE21396, C438S386000

Reexamination Certificate

active

07405439

ABSTRACT:
A memory cell structure comprises a first memory capacitor that is arranged in a first local area, and includes a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper electrode; a second memory capacitor that is spaced apart from the first memory capacitor and arranged in the first local area, and includes a second lower electrode, a second upper electrode, and a second dielectric oxide film interposed between the second lower electrode and the second upper electrode; and a first local interconnection layer.

REFERENCES:
patent: 5289416 (1994-02-01), Iwai et al.
patent: 5953619 (1999-09-01), Miyazawa et al.
patent: 2002/0045311 (2002-04-01), Mikawa

Affiliated with

Also associated with

Rating

Memory cell structure and semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cell structure and semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell structure and semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2774894