Memory cell sensing method and circuitry for bit line equalizati

Details Memory cell sensing method and circuitry for bit line equalizati Memory cell sensing method and circuitry for bit line equalizati

1997-04-07

1998-10-27

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365207, 365203, G11C 700

Patent

active

058286144

ABSTRACT:
A method and apparatus for sensing the state of a memory cell and equalizing bit line voltages without using ATD circuitry. One embodiment of the present invention is a memory device that includes a memory cell coupled to a pair of bit lines, a bit line load circuit coupled to the bit lines, an equalization circuit coupled to the bit lines, and a sense amplifier circuit having inputs coupled to the bit lines and an output coupled to the equalization circuit. The memory cell may be an SRAM cell with a pair of cross-coupled inverters. The equalization circuit may be an SRAM cell with a pair of inverters that are not cross coupled. The inputs of the inverters in the equalization circuit may receive signals output by the sense amplifier circuit, and the outputs of the inverters may be coupled to the pair of bit lines. The sense amplifier senses data output by the memory cell to the bit lines, and generates output signals. The equalization circuit receives the output signals and drives the bit lines with opposite data relative to the data output by the memory cell so as to equalize the bit lines.

REFERENCES:
patent: 4785427 (1988-11-01), Young
patent: 5432746 (1995-07-01), Guedj
patent: 5504443 (1996-04-01), Gross et al.
patent: 5525919 (1996-06-01), Phelan

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