Memory cell sense amplifier

Details Memory cell sense amplifier Memory cell sense amplifier

1998-10-14

2001-04-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185210

Reexamination Certificate

active

06219290

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory arrays, and in particular, the sensing of data from a non-volatile memory cell.
2. State of The Art
Erasable programmable read only memories (EPROM) or electrically erasable programmable read only memories (EEPROM) use a floating gate memory cell structure for storing data. The floating gate memory cell is programmed by altering the threshold voltage of a floating gate device in the memory cell. In general, memory cells are arranged in an array such that each cell has an associated bit-line and word-line. When accessed by an input address signal applied to the memory device, a memory cell having an altered/increased threshold voltage remains turned off resulting in a first voltage level being sensed from the memory cell. A memory cell having a non-altered threshold is turned on when accessed such that a second voltage level is sensed from the memory cell.
A common bit-line to a group of memory cells is coupled to a sense amplifier which functions to compare the voltage sensed from a memory cell to the voltage of a reference signal line and output a voltage representing the logic state stored in the memory cell.
FIG. 1
shows a simple circuit illustrating the manner in which a sense amplifier senses data from a floating gate memory cell structure. The current source I
REF
represents a reference cell current established in a reference circuit branch and the current source I
CELL
represents the addressed array cell current established in the array circuit branch. The voltage on the first input of the sense amplifier, V
SA1
, representing the logic state of the memory cell is V
DD
−I
CELL
·R
1
and the voltage on the second input of the sense amplifier, V
SA2
, corresponding to the reference voltage signal is V
DD
−I
REF
·R
2
. If the addressed cell has been programmed such that its threshold voltage Vt is increased to a high level the I
CELL
will be very small and consequently, V
SA1
>V
SA2
. On the other hand, if the addressed cell has not been programmed such that its threshold voltage is low and if I
CELL
is large enough, then V
SA1
<V
SA2
.
FIG. 2
shows a prior art sense amplifier structure which includes load devices M
0
and M
2
-M
4
which correspond to resistors R
1
and R
2
, respectively, a pre-charging circuit situated in the array circuit branch path including device M
1
and inverter XI
1
, a cell pre-charging circuit situated in the reference cell circuit branch path including device M
5
and inverter X
12
, column-select or bit line transistors MBL
0
-MBL
2
, a reference cell XREF
0
, floating gate devices XCELL
0
-XCELL
2
connected to different respective word lines WL
0
-WL
2
, and a comparator U
1
.
FIG. 2
does not show in detail the array structure. A detailed description of an example of an array architecture is disclosed in U.S. Pat. No. 5,526,307 assigned to the assignee of the present application.
The floating gate memory cells are programmed by adjusting the threshold voltages of the memory cell devices XCELL
0
-XCELL
2
. The reference cell XREF
0
has its control gate and floating gate tied together. Its threshold voltage is predetermined by the fabricating process such that when a signal RWL is applied the reference cell turns on and a predetermined current I
REF
is pulled through the reference cell circuit branch path.
In operation, if the input address to the device is decoded and the WL
0
and BL
0
signal lines are selected, the addressed column selector MBL
0
is turned on pulling the bit-line
20
coresponding to cell XCELL
0
LOW. With bit-line
20
LOW, the memory cell pre-charging circuit begins to pre-charge bit-line
20
and establishes a voltage (such as 1.2V) at the drain side of the addressed cell, (XCELL
0
in this case). The reference cell sensing path mirrors the operation of the memory cell sensing path. For instance, when the RWL signal is applied, the reference cell XREF
0
is turned on and the reference cell pre-charging circuitry also begins to pre-charge the reference signal line to establish a pre-charge voltage at the drain of the reference cell XREF
0
. The RWL signal may either be pulsed or constant. The voltage V
SA1
on the first input of the comparator U
1
coupled to the memory cell sensing path is V
SA1
=VDD−I
XCELL0
·R
M0
, and the voltage V
SA2
voltage on the second input of the comparator U
1
coupled to the reference cell sensing path is V
SA2
=VDD−I
XREF0
·R
M2∥M3∥M4
.
In order to ensure proper operation it is necessary to design the circuit such that when a memory cell is programmed to have a high threshold voltage (i.e. logic “1”), only a small amount of leakage current flows through the memory cell sensing path such that V
SA1
>V
SA2
. On the other hand, when the memory cell is not programmed and has a low threshold voltage (i.e. logic “0”), the circuit design must ensure that enough current flows through the memory cell sensing path such that V
SA1
<V
SA2
. In particular, if “1” is sensed (SAOUT=“1”), then V
SA1
>V
SA2
or VDD−I
XCELL0
·R
M0
>VDD−I
XREF0
·R
M2∥M3∥M4
which reduces to R
M0
/R
M2∥M3∥M4
<I
XREF0
/I
XCELL0
. The ratio of R
M0
/R
M2∥M3∥M4
is referred to as the sensing ratio. Hence, in order to ensure sensing accuracy the sensing ratio needs to be preserved.
The sequence of sensing the memory cell shown in
FIG. 2
is as follows and is shown in
FIGS. 3A and 4A
. In general, a chip enable signal is initially applied to the memory device at time T
1
. Alternatively, an ADDRESS transient signal may also be used to initiate the read operation wherein when an address is applied, an ADDRESS transient signal is generated. At the same time, or shortly thereafter, an address is applied to the input of an address decoder (not shown) of the memory device thereby initiating the decoding of the address. An interval of time &Dgr;T occurs in which the address is decoded. Once decoded a select signal is provided to the gate of one of the bit-line select transistors BL
0
-BLn and to one of the word-line select signal lines WL
0
-WLn. The address is decoded at time T
2
and depending on whether the addressed memory cell is programmed with a high threshold voltage or a low threshold voltage, V
SA1
begins to fall (
FIG. 3A
) or rise (FIG.
4
A). Finally, V
SA1
and V
SA2
are compared by comparator U
1
and the compared result is sent to an output buffer (not shown).
From the above description, the voltage on the sense amplifier input SA
1
only begins to rise or fall after address decoding is complete. Referring to
FIG. 3A
, assume “0” is to be sensed in the case in which the previous state of the memory cell was a “1” logic state. In general, the amount of time to decode the address &Dgr;T may be in the range of 15 nsec or more. Therefore, if the 15 ns latency can be reduced or eliminated, the read speed can be improved. A similar impact also occurs in sensing a “1” logic state in the case in which the previous state of the memory cell was a “0” logic state as shown in FIG.
4
A.
One prior art technique used to overcome the above problem is to equalize both sides of the differential sense amplifier. For instance U.S. Pat. No. 4,884,214 entitled “Nonvolatile Semiconductor Memory Device” uses an equalization circuit which is responsive to an address transition detection (ATD) signal to precharge both inputs of the differential sense amplifier to a high potential level during a non-read out period.
Similarly, in U.S. Pat. No. 5,524,094 entitled “Nonvolatile Memory Device with NAND Array” an equalizing circuit is used to equalize both inputs of the sense amplifier to an intermediate voltage of ½ VCC.
Finally, U.S. Pat. No. 5,559,737 entitled “Nonvolatile Semiconductor Memory Capable of Simultaneously Equalizing Bit Lines and Sense Lines” also equalizes both inputs of the sense amplifier using a bit-line biasing circuit and a dummy cell bit line biasing circuit.
In all three of these prior art technique

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