Memory cell reading circuit

Details Memory cell reading circuit Memory cell reading circuit

1991-12-19

1993-11-02

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, G11C 702

Patent

active

052589595

ABSTRACT:
A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and are furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistors are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, such as an EPROM cell, as compared to reading circuits previously used.

REFERENCES:
patent: 4884241 (1989-11-01), Tanaka
patent: 4947376 (1990-08-01), Arimoto
patent: 5010518 (1991-04-01), Toda
patent: 5062079 (1991-10-01), Tsuchida

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