Memory cell programmed using a temperature controlled set pulse

Details Memory cell programmed using a temperature controlled set pulse Memory cell programmed using a temperature controlled set pulse

2006-06-19

2008-11-25

Smith, Zandra (Department: 2822)

Static information storage and retrieval

Systems using particular element

Resistive

C365S218000, C365S221000

Reexamination Certificate

active

07457146

ABSTRACT:
A memory device includes a phase change memory cell and a circuit. The circuit is for programming the memory cell to a selected one of more than two states by applying a temperature controlled set pulse to the memory cell.

REFERENCES:
patent: 3530441 (1970-09-01), Ovshinsky
patent: 5296716 (1994-03-01), Ovshinsky et al.
patent: 6075719 (2000-06-01), Lowrey et al.
patent: 6487113 (2002-11-01), Park et al.
patent: 6512241 (2003-01-01), Lai
patent: 6625054 (2003-09-01), Lowrey et al.
patent: 6687153 (2004-02-01), Lowrey
patent: 6759267 (2004-07-01), Chen
patent: 6768665 (2004-07-01), Parkinson et al.
patent: 7012834 (2006-03-01), Cho et al.
patent: 7042760 (2006-05-01), Hwang et al.
patent: 7085154 (2006-08-01), Cho et al.
patent: 2004/0246804 (2004-12-01), Cho et al.
patent: 2004/0246808 (2004-12-01), Cho et al.
patent: 2005/0117387 (2005-06-01), Hwang et al.
patent: 2005/0117388 (2005-06-01), Cho et al.
patent: 20050046771 (2005-05-01), None
patent: 2004025659 (2004-03-01), None
S. Lal et al., “OUM-A 180 nm Nonvolatile Memory Cell Element Technology For Stand Alone And Embedded Applications,” 4 pgs., IEDM 2001.
Lai, Stefan, “Current Status Of The Phase Change Memory And Its Future,” pp. 10.1.1-10.1.4, IEDM 2003.
H. Horii et al., “An Edge Contact Type Cell For Phase Change RAM Featuring Very Low Power Consumption,” 2 pgs., VLSI, 2003.
ECD Ovonics, Research Report, Ovonic Unified Memory, 80 pgs., http://www.ovonics.com/PDFs/Elec Memory Research Report/OUM.pdf, 1999.
H. Horii et al., “A Novel Cell Technology Using N-Doped GeSbTe Films For Phase Change RAM,” 2 pgs., VLSI, 2003.
Y.N. Hwant, et al., “Full Integration And Reliability Evaluation Of Phase-Change RAM Based On 0.24 μm-CMOS Technologies,” 2 pgs., VLSI, 2003.
Jeong et al., “Switching Current Scaling And Reliability Evaluation In Pram,” pp. 28-29, NVSMW, 2004.
G. Atwood et al., http://www.intel.com/design/flash/isf/overview.pdf, 8 pgs., 1997.
T. Sakamoto et al., “A Nonvolatile Programmable Solid Electrolyte Nanometer Switch,” 10 pgs., ISSCC, 2004.
H.R. Oh et al., “Enhanced Write Performance Of A 64Mb Phase Change RAM,” 3 pgs., ISSCC, 2005.
T. Lowrey et al., “Characteristics Of OUM Phase Change Memory Materials And Devices For High Density Nonvolitile Commodity And Embedded Memory Applications,” 7 pgs., MRS Sump. Proc. 803, 101, 2004.
Korean Office Action for Korean Application No. 10-2007-0059789 mailed May 30, 2008 (4 pages).

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