Memory cell of SRAM used in environmental conditions of high-ene

Details Memory cell of SRAM used in environmental conditions of high-ene Memory cell of SRAM used in environmental conditions of high-ene

1991-09-10

1994-04-05

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365190, G11C 1140

Patent

active

053011465

ABSTRACT:
A memory cell of a static semiconductor memory device includes first and second inverters, first and second variable resistors and first and second transfer transistors. The first variable resistor is connected between an output terminal of the first inverter and an input terminal of the second inverter. The second variable resistor is connected between an output terminal of the second inverter and an input terminal of the first inverter. The first transfer transistor has a current path connected between the output terminal of the first inverter and a first bit line and a gate connected to a word line. The second transfer transistor has a current path connected between the output terminal of the second inverter and a second bit line and a gate connected to the word line. A control circuit controls the resistances of the first and second variable resistors, and the resistances of the first and second variable resistors are controlled to be reduced when a memory cell is selected in the write-in cycle and they are increased when the memory cell is not selected.

REFERENCES:
patent: 4725981 (1988-02-01), Rutledge
patent: 4766572 (1988-08-01), Kobayashi
patent: 4797804 (1989-06-01), Rockett, Jr.
patent: 4956814 (1990-09-01), Houston
Kohler et al., "SEU Characterization of Hardened CMOS SRAMS Using Statistical Analysis of Feedback Delay In Memory Cells," IEEE Transactions On Nuclear Science, vol. 36, No. 6, pp. 2318-2322 (Dec. 1989).

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