Memory cell, nonvolatile memory device and control method...

Details Memory cell, nonvolatile memory device and control method... Memory cell, nonvolatile memory device and control method...

2002-02-28

2003-11-11

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S171000, C365S145000

Reexamination Certificate

active

06646909

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a memory cell of shadow RAM (Random Access Memory) employing ferroelectric capacitors, a nonvolatile memory device employing the memory cells, and a control method for the memory cell, and in particular, to shadow RAM, in which high-speed reading/writing from/to SRAM cells is realized when power is supplied thereto and nonvolatile memory by use of ferroelectric capacitors is realized when power is not supplied thereto, that is capable of operating with high reliability even when the power supply voltage is low.
DESCRIPTION OF THE RELATED ART
A variety of shadow RAMs in which ferroelectric capacitors and SRAM cells are combined have been proposed so far. When power is being supplied, the shadow RAM stores information in its SRAM cells, offering high-speed reading/writing capability of the level of ordinary SRAM. Further, the shadow RAM realizes nonvolatile memory when power is not supplied thereto, by transferring data which has been stored in the SRAM cells to ferroelectric capacitors (as polarization directions of the ferroelectric capacitors) before the power is shut off (storing operation). In short, the shadow RAM employing ferroelectric capacitors is a storage device having two advantages: nonvolatility of ferroelectric memory and high-speed operation of SRAM.
FIG. 1
is a circuit diagram showing the composition of a memory cell of shadow RAM employing ferroelectric capacitors which has been disclosed in Japanese Patent Application Laid-Open No.2000-293989. In the memory cell of
FIG. 1
, a flip-flop
3
is formed by connecting two inverters
1
and
2
in ring connection (the input/output terminal of an inverter is connected to the output/input terminal of the other inverter). Two memory nodes Q
0
and Q
1
of the flip-flop
3
are connected to a negative bit line BLN and a positive bit line BLP respectively via NMOS transistors MO and M
1
which function as transfer gates. The positive
egative bit lines BLP and BLN are used as a pair, and a sense amplifier (unshown) for comparing the voltages of the positive
egative bit lines BLP and BLN are connected to the bit lines.
To the bit lines BLP and BLN, a writing circuit (unshown) for connecting selected bit lines to the ground potential when data writing is carried out and a precharge circuit (unshown) for precharging the bit lines to a power supply voltage or the ground potential are also connected. The gates of the NMOS transistors MO and M
1
are connected to a common word line WL. The word lines WL are connected to a decoder circuit (unshown). The decoder circuit selectively drives a word line as the target of access according to an address signal. Ferroelectric capacitors F
0
and F
1
, whose lower terminals shown in
FIG. 1
are connected to a common plate line PL, are connected to the memory nodes Q
0
and Q
1
respectively. The plate lines PL are connected to a plate line driving circuit
4
. When the power is supplied to the shadow RAM, the plate line driving circuit
4
holds the voltages of the plate lines PL at Vcc/2 except in the storing operation and the recall operation of the shadow RAM.
In the following, the operation of the conventional shadow RAM employing ferroelectric capacitors will be explained in detail. Needless to say, data reading/writing from/to the flip-flops
3
of the shadow RAM are carried out in the same way as in general conventional SRAM. In idle states of the shadow RAM (in which no reading/writing is carried out), data stored in the flip-flops
3
is maintained and preserved by discharging (dropping the voltages of) all the word lines WL, precharging the bit lines to a proper voltage, and stopping the writing circuit.
When data is written into a flip-flop
3
, the address decoder circuit drives (raises the voltage of a proper word line WL corresponding to the flip-flop
3
, and simultaneously, the writing circuit sets one of the positive
egative bit lines BLP and BLN (corresponding to the flip-flop
3
) to a low level depending on the data to be written into the flip-flop
3
. By the increase of the voltage of the driven word line WL, the MOS transistors MO and M
1
turn on. Since the driving power of the writing circuit is far larger than that of the inverters
1
and
2
, the voltage of a memory node (Q
0
or Q
1
) that is connected to the bit line (that is set to the low level by the writing circuit) via a MOS transistor is dropped to the ground potential. At the same time, the voltage of the other memory node (Q
1
or Q
0
) is raised to the power supply voltage and thereby the flip-flop
3
is stabilized.
Data readout from a flip-flop
3
is carried out by precharging the bit line pair (BLP and BLN) corresponding to the flip-flop
3
to a high level, selecting and driving a proper word line corresponding to the flip-flop
3
, and amplifying a voltage difference occurring between the bit line pair by use of a sense amplifier. When the voltage of the word line WL is raised, a MOS transistor (M
0
or M
1
) that connects the low-level memory node (Q
0
or Q
1
) and the bit line (BLN or BLP) turns on and thereby the voltage of the bit line (BLN or BLP) starts falling. The other bit line (BLP or BLN) keeps its high level since the MOS transistor (M
1
or M
0
) does not turn on. By detecting the voltage difference between the bit line pair by use of the sense amplifier, data stored in the flip-flop
3
can be read out.
In the following, the storing operation of the shadow RAM memory cell of
FIG. 1
will be explained referring to
FIGS. 2 and 17
.
FIG. 17
shows the hysteresis characteristics of the ferroelectric capacitors F
0
and F
1
on a Q-V plane.
FIG. 2
is a timing chart showing the change of voltage of each part of the memory cell of
FIG. 1
during the storing operation. When the power is shut off, data which has been stored in the flip-flop
3
is transferred to the ferroelectric capacitors F
0
and F
1
and stored as polarization directions of the ferroelectric capacitors. The operation is called “storing”. The storing is activated by a trigger such as a drop of the power supply voltage or a storing signal which is supplied before the power is shut off. The storing is carried out as follows.
The voltage of the plate line PL when the storing operation is started is Vcc/2. Therefore, depending on the data stored in the flip-flop
3
, a voltage −Vcc/2 is applied to a ferroelectric capacitor that is connected to a memory node holding 0V, whereas a voltage Vcc/2 is applied to a ferroelectric capacitor that is connected to a memory node holding the power supply voltage (Vcc).
Incidentally, the aforementioned “voltage” that is applied to each ferroelectric capacitor (F
0
, F
1
) is defined as a voltage difference between the upper terminal shown in
FIG. 1
(which is connected to the memory node Q
0
or Q
1
) and the lower terminal (which is connected to the plate line PL), that is, the voltage of the upper terminal relative to the lower terminal.
Subsequently, the voltage of the plate line PL is raised to Vcc. By the increase of the plate line voltage, the terminals of the latter ferroelectric capacitor (to which the voltage Vcc/2 has been applied) will have the same voltage Vcc, thereby the voltage that is applied to the ferroelectric capacitor changes to 0V. To the other ferroelectric capacitor, a voltage −Vcc is applied, and thereby the status of the ferroelectric capacitor gets to a point C in the hysteresis loop of FIG.
17
.
Subsequently, the voltage of the plate line PL is dropped to 0V, thereby a voltage Vcc is applied to the ferroelectric capacitor that is connected to the memory node holding Vcc and thereby the status of the ferroelectric capacitor gets to a point A in the hysteresis loop of FIG.
17
. At the same time, the ferroelectric capacitor that has been at the point C moves to a point D and holds negative remanent polarization.
Finally, the power is shut off. After the power shutoff, the voltage of each memory node converges on the ground potential. Consequently, the ferroelectric capacito

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