Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-09
2001-11-13
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S303000, C257S306000, C257S327000
Reexamination Certificate
active
06316799
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory cell of a DRAM (Dynamic Random Access Memory) and, more particularly, to a memory cell having a structure in which a capacitor and a transistor connected thereto are stacked on a semiconductor substrate.
2. Description of the Background Art
A DRAM comprises a memory cell array serving as a storage area for storing a large amount of information, and a peripheral circuit part for causing the memory cell array to perform a predetermined input/output operation. The memory cell array has a plurality of memory cells arranged in an array and each corresponding to a minimum storage unit. A memory cell basically comprises a capacitor and a MOS (Metal Oxide Semiconductor) transistor (cell transistor) connected to the capacitor. Data values “0” and “1” (or vice versa) are associated with whether or not the capacitor stores a predetermined electric charge, and are provided for processing of the stored information.
FIG. 50
is a circuit diagram of an equivalent circuit of a typical DRAM memory cell
200
A. The memory cell
200
A comprises a capacitor
201
and a cell transistor
202
. The capacitor
201
has a first end receiving a fixed potential, e.g. a ground potential, and a second end connected to a bit line
203
through the cell transistor
202
. The cell transistor
202
has a gate electrode connected to a word line
204
. A sense amplifier
205
connected to the bit line
203
is also shown in FIG.
50
. The cell transistor
202
further has a pair of electrodes for establishing a connection between the bit line
203
and the capacitor
201
. The pair of electrodes of the cell transistor
202
function as a source of carriers or function to drain carriers out of the cell transistor
202
, and therefore are referred to hereinafter as source/drain.
In the memory cell
200
A, a leakage current flows between a semiconductor substrate in which the transistor
202
is formed and the capacitor
201
. The leakage current varies the electric charge on the capacitor
201
to give rise to an error of the information stored in the capacitor
201
. To compensate for such variations in electric charge, the DRAM memory cells perform a refresh operation.
In the refresh operation, the sense amplifier
205
reads information from the capacitor
201
, and a write operation is conducted. If it is judged that the capacitor
201
is charged, the sense amplifier
205
replenishes the capacitor
201
with a new electric charge. If it is judged that the capacitor
201
is not charged, the sense amplifier
205
eliminates the electric charge on the capacitor
201
.
However, the refresh operation increases the power consumption of a chip with the increase in the number of memory cells. Furthermore, a large leakage current from the capacitor requires the refresh operation to be performed frequently. For example, conventional DRAMs must perform the refresh operation upon the information stored in all memory cells in a relatively short cycle of the order of one millisecond to hundreds of milliseconds.
While the refresh operation is being performed, the memory cells cannot read out the information stored therein. In view of this fact, the frequent refresh operation decreases the efficiency with which the information stored in the memory is used relative to the operating time.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a memory cell comprises: a cell transistor having a pair of source/drain regions and a gate electrode; a first semiconductor layer provided on one of the source/drain regions and having a first impurity concentration ranging from about 5×10
17
/cm
3
to about 1×10
20
/cm
3
; a second semiconductor layer provided on the first semiconductor layer and having a second impurity concentration of not less than about 4×10
20
/cm
3
; a dielectric layer provided on the second semiconductor layer; and an electrode, in conjunction with the dielectric layer and the second semiconductor layer, constituting a capacitor, the second semiconductor layer serving as a counter electrode to the electrode.
Preferably, according to a second aspect of the present invention, the memory cell of the first aspect further comprises an interlayer insulation film for providing isolation between the capacitor and the cell transistor, wherein the first semiconductor layer includes a storage node extending through the interlayer insulation film, and a pad between the storage node and the one of the source/drain regions.
Preferably, according to a third aspect of the present invention, in the memory cell of the first or second aspect, the first semiconductor layer is depleted during a pause period over which the capacitor holds electric charge without being refreshed.
According to a fourth aspect of the present invention, a memory cell comprises: a cell transistor having a pair of source/drain regions and a gate electrode; a conductor provided on one of the source/drain regions and having a cavity therein; and a capacitor formed on the conductor.
According to a fifth aspect of the present invention, a memory cell comprises: a cell transistor having a pair of source/drain regions and a gate electrode; a first interlayer insulation film formed on the cell transistor; a first conductor extending through the first interlayer insulation film and provided on one of the source/drain regions; a second interlayer insulation film isolated from the cell transistor by the first interlayer insulation film; a second conductor extending through the second interlayer insulation film and formed on the first conductor; and a capacitor connected to the first conductor through the second conductor.
According to a sixth aspect of the present invention, a memory cell comprises: a first transistor having a pair of source/drain regions provided in an upper surface of a semiconductor substrate, and a gate electrode opposed to the semiconductor substrate with a first insulation film therebetween; a capacitor opposed to the first transistor with an interlayer insulation film therebetween in a depth direction of the semiconductor substrate, the capacitor being connected to one of the source/drain regions of the first transistor; and a second transistor disposed in the interlayer insulation film between the one of the source/drain regions of the first transistor and the capacitor, the second transistor having a pair of source/drain regions stacked in the depth direction of the semiconductor substrate.
Preferably, according to a seventh aspect of the present invention, in the memory cell of the sixth aspect, the first transistor and the second transistor are of the same conductivity type. The gate electrode of the first transistor has a sidewall covered with a second insulation film, and the pair of source/drain regions of the second transistor are disposed adjacent to the gate electrode of the first transistor with the second insulation film therebetween.
Preferably, according to an eighth aspect of the present invention, in the memory cell of the sixth aspect, the second transistor further has a gate electrode provided over the first transistor, and a second insulation film for covering a sidewall of the gate electrode of the second transistor. The pair of source/drain regions of the second transistor are disposed adjacent to the gate electrode of the second transistor with the second insulation film therebetween.
According to a ninth aspect of the present invention, a method of controlling a memory cell as defined in the eighth aspect comprises the step of bringing the second transistor into conduction before bringing the first transistor into conduction.
Preferably, according to a tenth aspect of the present invention, the memory cell of the sixth aspect further comprises a semiconductor layer for establishing a connection between one of the source/drain regions of the second transistor and the capacitor, wherein the second transistor further has a second insulation film disposed adjacent to the pair of source
Loke Steven
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Vu Hong Kim
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