Memory cell leakage reduction

Details Memory cell leakage reduction Memory cell leakage reduction

2002-12-19

2004-04-20

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S203000

Reexamination Certificate

active

06724649

ABSTRACT:

BACKGROUND
1. Technical Field
An embodiment of the invention relates generally to integrated circuits, and in particular relates to reducing leakage in memory circuits.
2. Description of the Related Art
Memory circuits are typically organized in a row and column matrix of memory cells, in which a line connecting a row of cells (e.g., a word line) and a line connecting a column of cells (e.g., a bit line) are both activated. The cell that is connected to both lines is thereby activated and may be read from or written into. The remaining cells do not have both of their connecting lines activated and therefore do not respond to attempts to read or write. In a read operation in a typical memory, the selected bit line is pre-charged (brought to voltage Vcc) before the selected word line is activated. When the word line is activated, the selected cell will pull down the voltage on the pre-charged bit line if the cell was storing a particular value (e.g., a logic 1), but will not pull down the voltage if the cell was storing the opposite value (e.g., a logic 0), thus permitting the stored value to be determined. Some memories use differential bit line sensing, in which a pair of bit lines is connected to the cells in a given column, and both bit lines are pre-charged. When the word line is activated, the selected cell will pull down the voltage on one of the two per-charged bit lines if a logic 0 is stored in the cell, while the cell will pull down the voltage on the other of the two pre-charged bit lines if a logic 1 is stored in the cell.
For both the single-ended and differential bit line arrangements, the non-selected cells may experience a low signal level on their (non-selected) word lines, and a high on the bit line that is not pulled down. This combination may cause the non-selected cells to experience a leakage current. Although the leakage current for a single cell may be small, the total leakage current for the entire column is equal to the sum of the leakage currents for all the non-selected memory cells (i.e., the total number of memory cells in the column−1). Since many cells may be connected in a column, this can represent a substantial amount of leakage current onto the bit lines. In the case of differential sensing it may interfere with the ability of the sensing circuits to detect the state of the selected memory cell, since the drive current from the selected cell must be detectably greater than the sum of the leakage currents for all the non-selected cells in the column.


REFERENCES:
patent: 5410506 (1995-04-01), Ferrant et al.
patent: 5757702 (1998-05-01), Iwata et al.
patent: 6181608 (2001-01-01), Keshavarzi et al.
patent: 6373760 (2002-04-01), Ohbayashi
patent: 6552925 (2003-04-01), Brooks
patent: 6556471 (2003-04-01), Chappell et al.

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