Memory cell layout structure with outer bitline

Details Memory cell layout structure with outer bitline Memory cell layout structure with outer bitline

2008-09-12

2010-10-19

Le, Thao (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S393000, C257S350000

Reexamination Certificate

active

07816740

ABSTRACT:
An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a first storage node, a second PU/PD transistor for a second storage node, and driver, cell pass, and buffer pass transistors. The memory cell includes a first gate electrode region for the first PU/PD and driver transistors, a second gate electrode region for the cell pass and buffer pass transistors, and a third gate electrode region for the second PU/PD transistor. The third gate electrode region and the cell pass transistor are coupled to the first storage node and the first gate electrode region is coupled to the second storage node. The buffer pass and driver transistors are coupled to a source/drain path of the cell pass transistor and the buffer pass transistor is coupled between a bitline (BL) node and the driver transistor.

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Ted Houston, U.S. Appl. No. 12/209,418, “Storage Cell Having Buffer Circuit for Driving the Bitline,” filed Sep. 12, 2008.
Ted Houston, U.S. Appl. No. 12/209,657, “Dual Node Access Storage Cell Having Buffer Circuits,” filed Sep. 12, 2008.

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