Memory cell isolation

Details Memory cell isolation Memory cell isolation

2002-05-22

2004-10-05

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S173000, C365S177000, C365S179000, C365S055000, C365S072000

Reexamination Certificate

active

06801450

ABSTRACT:

BACKGROUND
FIG. 1A
illustrates a non-volatile resistive memory cell according to the related art. The memory cell illustrated in
FIG. 1A
includes a magnetic random access memory (MRAM) cell
10
that is made up of a hard ferromagnetic layer
15
that has a fixed magnetic orientation, a tunneling barrier layer
20
, and a soft ferromagnetic layer
25
. The magnetic orientation of the soft ferromagnetic layer
25
may be switched between a direction parallel to the magnetic orientation of the hard ferromagnetic layer
15
(the parallel state) and a direction anti-parallel with the magnetic orientation of the hard ferromagnetic layer
15
(the anti-parallel state).
The effective resistance of the MRAM cell
10
(i.e. the amount of current allowed to pass through the tunneling barrier layer
20
) depends upon whether the MRAM cell
10
is in the parallel or the anti-parallel state. Further, when a voltage is applied across the MRAM cell
10
, an MRAM cell
10
in either a high or a low effective resistance allows for either a high or a low amount of current to flow through the MRAM cell
10
. Hence, the high and low effective resistances can represent a “1” and a “0” data bit, respectively, and these data bits may be read from the MRAM cell
10
by monitoring the amount of current that passes through the MRAM cell
10
.
In
FIG. 1A
, a two-layer diode
30
is electrically connected to the MRAM cell
10
and both the two-layer diode
30
and the MRAM cell
10
are positioned between a first metal layer
35
and a second metal layer
40
. The two-layer diode
30
includes a first p-doped semiconductor layer
45
and a first n-doped semiconductor layer
50
. The two-layer diode
30
restricts current flow in one direction across the non-volatile resistive memory cell.
The solid curve shown in
FIG. 1B
illustrates the current that flows through the two-layer diode
30
as a variety of voltages are applied to the two-layer diode
30
. At low voltages, and at voltages that place a reverse bias across the two-layer diode
30
, little current flows through the two-layer diode
30
. In contrast, when a forward bias is applied to and increased across the two-layer diode
30
, the current flowing through the two-layer diode
30
also increases. Thus when the two-layer diode
30
is connected to an MRAM cell
10
, a forward bias across the two-layer diode
30
allows current to flow through the MRAM cell
10
. However, a reverse bias across the two-layer diode
30
passes less current and therefore electrically isolates the MRAM cell
10
.
One disadvantage of using a two-layer diode
30
to electrically isolate an MRAM cell
10
is that the two-layer diode
30
nonetheless allows a significant amount of current to flow through the MRAM cell
10
when a reverse bias is applied. Another disadvantage is that a forward bias across the two-layer diode
30
allows current to increase relatively slowly as a function of added voltage.
A disadvantage of the device illustrated in
FIG. 1A
is the high voltage drop that occurs across the two-layer diode
30
when a forward biasing voltage is applied across the non-volatile resistive memory cell. Further, since both the forward bias voltage and the series resistance of the two-layer diode
30
are strong functions of current, there may be a wide range of two-layer diode
30
forward voltage drops caused as a wide range of forward currents are applied to the two-layer diode
30
. Hence, it becomes difficult to deconvolute the voltage drop due to the presence of the two-layer diode
30
from the voltage drop due to the MRAM cell
10
and data bits are not read as easily.
In addition, the two-layer diode
30
illustrated in
FIG. 1A
is typically a thin-film diode and therefore may leak a substantial amount of current. This phenomenon is partially illustrated in the lower, left quadrant of the graph in
FIG. 1B
, where reverse biasing across the two-layer diode
30
nonetheless allows some current flow. When many devices such as the device illustrated in
FIG. 1A
are electrically connected together in an array, diode leakage currents from many other devices in the array (that are electrically connected in parallel with the selected device) limit the signal resolution and increase noise when detecting data stored on the selected device.
SUMMARY
A memory cell that includes an isolation element and a resistive component electrically connected to the isolation element. The isolation element includes a first layer doped with a first type of charge, a second layer positioned adjacent to the first layer and doped with a second type of charge, a third layer positioned adjacent to the second layer and doped with the first type of charge, and a fourth layer positioned adjacent to the third layer and doped with the second type of charge.
A memory array that includes a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines at a plurality of cross points, and a plurality of memory cells. A memory cell in the plurality of memory cells may be located at a cross point of a first word line and a first bit line. The memory cell may include an isolation element and a resistive component electrically connected to the isolation element. The isolation element may include a first layer doped with a first type of charge, a second layer positioned adjacent to the first layer and doped with a second type of charge, a third layer positioned adjacent to the second layer and doped with the first type of charge, and a fourth layer positioned adjacent to the third layer and doped with the second type of charge.
A method of operating a data storage device. The device may include word lines, bit lines, and a memory array of memory cells, the memory cells being located at cross points of word lines and bit lines. The method may include the step of selecting a memory cell wherein the memory cell includes an isolation element and a resistive component. The method may also include activating the isolation element by rapidly applying a forward bias across the isolation element, and causing a current to flow through the selected memory cell.


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