Memory cell integrated structure with corresponding biasing...

Details Memory cell integrated structure with corresponding biasing... Memory cell integrated structure with corresponding biasing...

2000-09-29

2001-10-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240

Reexamination Certificate

active

06304490

ABSTRACT:

TECHNICAL FIELD
This invention relates to an integrated structure for memory cells.
The invention also relates to a device for biasing a memory cell having at least one substrate bias terminal associated therewith.
The invention concerns, particularly but not exclusively, the use of the integrated structure for memory cells and the biasing device in a condition of low supply voltage, and the description herein will make reference to this field of application for convenience of explanation.
BACKGROUND OF THE INVENTION
As is well known, a non-volatile memory cell is read by means of a current-to-voltage conversion, suitably biasing the cell in a way that, when the stored information has a first logic value of “1”, the cell is able to draw current.
In particular, for a proper memory cell reading operation, the current drawn by the cell should be greater than a preset value, teamed the reference value Iref, which is usually a function of the supply voltage Vcc.
On the other hand, where the information has a second logic value of “
0
”, the current drawn should be less than the reference value Iref
The latest generation memory devices use values of the supply voltage Vcc ever so much smaller that a proper reading of memory cells becomes increasingly more of a problem.
In fact, discriminating between an erased cell (first logic value “1”) and a written cell (second logic value “0”) is only possible if the erased cell is able to draw a larger current than the reference value Iref, and this can only be if the voltage applied to the gate terminal of the cell in the reading phase, which is normally the same as the supply voltage Vcc, is higher than the cell threshold voltage.
For proper performance of the reading operation, there are available a number of circuit modifications which are primarily concerned with distributing the values of the threshold voltages Vth of the erased memory cells. The highest value of a threshold voltage Vth for an erased cell currently sets in the 2.5V range.
SUMMARY OF THE INVENTION
An embodiment of this invention provides an integrated structure and a biasing device for memory cells, which have such constructional and functional features as to overcome the constraints from the distribution of the threshold voltage values which still beset prior art memory devices.
Specifically, the integrated structure for memory cells is formed over a semiconductor substrate doped with a first dopant type and including at least one memory cell, in turn formed in a conductive well provided in said semiconductor substrate and doped with a second dopant type, said conductive well having an additional substrate well formed therein which is doped with the first dopant type and comprises active areas of the memory cell.
The biasing device of the embodiment includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell. The circuitry block also includes a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.
An embodiment of the invention is also directed to a method that only modifies the value of the threshold voltage of a memory cell during the reading phase, by body effect.
In particular, this concept can be applied to the instance of memory cells formed by a triple well process. In fact, the presence of a triple well enables a cell matrix to be placed within a substrate well which represents a region of isolation from a substrate portion where the external circuitry of the matrix is accommodated.
In this way, the different substrates can be biased at different voltages, thereby allowing the body effect to be restricted to just the reading phase.
The features and advantages of the invention can be better understood by having reference to the following description of embodiments thereof, to be read as non-limitative examples in conjunction with the accompanying drawings.


REFERENCES:
patent: 4825142 (1989-04-01), Wang
patent: 5243559 (1993-09-01), Murai
patent: 5461338 (1995-10-01), Hirayama et al.
patent: 5548146 (1996-08-01), Kuroda et al.
patent: 5576995 (1996-11-01), Sato et al.
patent: 0 714 099 A1 (1996-05-01), None

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