Memory cell insensitive to collisions of heavy ions

Details Memory cell insensitive to collisions of heavy ions Memory cell insensitive to collisions of heavy ions

1995-12-11

1997-06-17

Nguyen, Tan T.

Static information storage and retrieval

Systems using particular element

Flip-flop

G11C 1140

Patent

active

056403410

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to static memory cells and more particularly to memory cells whose state is not modified by the collision of a heavy ion on a sensitive area of the cell.
Electronics devices may, under some conditions, especially in space, be subjected to particle bombardments, especially heavy ion bombardments. When the drain region of a MOS transistor biased in a predetermined direction is crossed by a heavy ion, the MOS transistor generates a parasitic pulse at its drain. Such a parasitic phenomenon, usually named "upset", may cause impairing effects, especially the state of the memory cell may be changed by the action of the parasitic pulse on various transistors of the cell.
FIG. 1A represents the structure of a conventional memory cell of the differential type (i.e., a cell that stores data as two complementary states). This cell is used to fabricate any type of flip-flops, registers and Static Random Access Memories (SRAMs). An SRAM, unlike a dynamic memory (DRAM), is a memory that does not require refreshing signals to maintain its state.
The cell includes two head-to-tail connected inverters. The first inverter comprises a P-channel MOS transistor MP1 and an N-channel MOS transistor MN1 whose drains are connected together and constitute the output Q of the inverter. The sources of transistors MP1 and MN1 are connected to a high voltage Vdd and to a low voltage Vss, respectively. The second inverter comprises a P-channel MOS transistor MP2 and an N-channel MOS transistor MN2 connected like transistors MN1 and MP1, respectively. The drains of transistors MP2 and MN2 are connected together and constitute the output Q* of the second inverter. The gates of transistors MP2 and MN2 (the input of the second inverter) are connected to the output Q of the first inverter. The gates of transistors MP1 and MN1 (the input of the first inverter) are connected to the output Q* of the second inverter.
An N-channel MOS transistor MN3 connects the output Q to a data line D. An N-channel MOS transistor MN4 connects the output Q* to a data line D*. Lines D and D* convey differential data (the states of lines D and D* are complementary) to be read and to be stored in the memory cell. The gates of transistors MN3 and MN4 are controlled by a read/write line RW.
FIG. 1B represents the cell of FIG. 1A in its initial state. Nodes having a voltage close to the low voltage Vss are indicated by 0s; nodes having a voltage close to the high voltage Vdd are indicated by 1s. It is assumed that the cell is in a steady state, i.e., that the read/write line is in an inactive state, 0. To better illustrate the operation of this memory cell, transistors in the off state are represented by empty areas.
The initial state represented in FIG. 1B is such that outputs Q and Q* are set to 1 and 0, respectively. Transistors MN1, MP2, MN3, and MN4 are off, and transistors MP1 and MN2 are conductive.
To read the state of this cell, line RW is actuated, which turns on transistors MN3 and MN4 that transmit the state 1 of output Q to line D and the state 0 of output Q* to line D*, respectively.
To change the state of the cell, line RW is actuated; a state 0 is provided to line D and a state 1 is provided to line D*. The 0 present on line D forces output Q to 0. The state 0 of output Q, provided to the gates of transistors MP2 and MN2, turns off transistor MN2 and turns on transistor MP2. Thus, the output Q* is set to 1, which turns off transistor MP1 and turns on transistor MN1 that maintains the state 0 at output Q. A symmetrical effect is obtained with line D* which forces output Q* to 1. The memory cell is then in a new steady state.
Lines D and D* must be controlled, when the state of a cell changes, by a relatively high current since it is desired, for example, to pull the state of output Q down to Vss whereas transistor MP1 pulls this state up to Vdd, and it is also desired to pull the state of the output Q* up to Vdd, whereas transistor MN2 pulls this state down to Vss. For writing in the memory cell, buffers should be provided

REFERENCES:
patent: 3928773 (1975-12-01), Oguey
patent: 4387444 (1983-06-01), Edwards
patent: 4403306 (1983-09-01), Tokushige et al.
patent: 4852060 (1989-07-01), Rockett, Jr.
patent: 5075581 (1991-12-01), Kamata

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